Where communities thrive


  • Join over 1.5M+ people
  • Join over 100K+ communities
  • Free without limits
  • Create your own community
People
Activity
  • 18:00

    github-actions[bot] on nightly

    synth/elab-vhdl_values: use a p… vhdl-canon: remove unused canon… synth-vhdl_expr: avoid a memocy… and 6 more (compare)

  • 17:21

    tgingold on master

    synth/elab-vhdl_values: use a p… vhdl-canon: remove unused canon… synth-vhdl_expr: avoid a memocy… and 6 more (compare)

  • 11:10
    Paebbels commented #2065
  • 11:01
    Paebbels commented #2065
  • 11:00
    gncemre23 commented #2065
  • 04:08
    tgingold commented #2065
  • 04:08
    tgingold reopened #2065
  • May 21 17:00
    Paebbels commented #2065
  • May 21 16:13
    gncemre23 closed #2065
  • May 21 16:12
    gncemre23 commented #2065
  • May 21 15:22
    gncemre23 edited #2065
  • May 21 15:06
    umarcor labeled #2065
  • May 21 15:06
    umarcor labeled #2065
  • May 21 15:03
    gncemre23 opened #2065
  • May 20 22:56
    umarcor opened #2064
  • May 18 17:58

    github-actions[bot] on nightly

    elab-vhdl_context: remove cur_s… synth-vhdl_stmts: add comments … synth-vhdl_stmts: avoid a crash… and 1 more (compare)

  • May 18 17:17
    umarcor milestoned #2063
  • May 18 17:16
    tgingold closed #2063
  • May 18 17:16

    tgingold on master

    elab-vhdl_context: remove cur_s… synth-vhdl_stmts: add comments … synth-vhdl_stmts: avoid a crash… and 1 more (compare)

  • May 18 11:42
    cderrien commented #2063
GlenNicholls
@GlenNicholls

Hmmm -frelaxed seems to do the job

I use modelsim and much of my style would be annoying to change if I didn't have the option of using that flag in GHDL when licenses are not available. I generally wouldn't revise unless synthesis gives an error

Julien FAUCHER
@suzizecat
Well, sure, but since I'm working primarily with GHDL (using VSCode) then porting it to ISE when it will be done, I would rather stay as strict as possible.
GlenNicholls
@GlenNicholls

Well, sure, but since I'm working primarily with GHDL (using VSCode) then porting it to ISE when it will be done, I would rather stay as strict as possible.

That's understandable! It seems all the EDA tools have different default settings for the LRM compliance depending on what users complain about, so it can be a very thin line. The best way is to be strict and comply yourself as this will be a tooling bug if they don't comply with that style. It's tough with the older standards, though, and I totally get it

eine
@eine
@suzizecat, do you know you can use ghdl --synth to "translate" your VHDL 2008 to a VHDL 1993 netlist that ISE accepts?
Julien FAUCHER
@suzizecat
:heart_eyes: Oh ?
eine
@eine
That's the most valuable feature of GHDL's synthesis ATM, from my point of view.
Julien FAUCHER
@suzizecat
However, will I be able to have a blackbox (like a ROM which will be replaced by a generated IP in ISE ?)
eine
@eine
Cannot reply with certainity, but I'd say that you can. GHDL should keep the black boxes.
Julien FAUCHER
@suzizecat
Hmmm is there some kind of documentation on ghdl --synth ?
eine
@eine
It is possible to have black boxes to then fit verilog modules through yosys. So, sticking in VHDL should be easier...
Julien FAUCHER
@suzizecat
Oh ! That's new :3
eine
@eine
Yes, 2-3 weeks?
Julien FAUCHER
@suzizecat
New to me then
Alexandre A. Muller
@alemuller
@suzizecat I think you can use type qualifier.
Alexandre A. Muller
@alemuller
subtype t_instr is std_logic_vector(7 downto 4);
case t_instr'(r_instruction_cmd) is
Julien FAUCHER
@suzizecat
@eine To have a blackbox, do I just ditch my "ghdl-behav" rom entity then run synth ?
On fresh master, synthesis report few design-related errors then crash btw
eine
@eine
@suzizecat I think that you might only need to define a component, not even provide the behavioural model. However, I have not tried. The closer I have seen is https://github.com/ghdl/ghdl-yosys-plugin/blob/master/library/ecp5u/components.vhdl, which is what @hackfin has been using to instantiate primitives from Lattice.

On fresh master, synthesis report few design-related errors then crash btw

Yes, synthesis is an experimental feature yet. In fact, it is very active and multiple related issues are being fixed every day.

Julien FAUCHER
@suzizecat
Are reported errors messages kind of standard and/or is there a way to find some information for troubleshoot ? (even though "multiple assignements for xxx" is quite straightforward, "latch inferred for net xxx" is less clear to me)
eine
@eine
Are those errors reported by ghdl --synth?
Julien FAUCHER
@suzizecat
yep
I have
julien@R220:~/Projets/VHDL/MPU_KAT$ ghdl --synth --std=08 --workdir=work mpu
rtl/mpu.vhdl:200:5:error: latch infered for net "query_bus"
rtl/mpu.vhdl:15:9:error: multiple assignments for offsets 0:23
rtl/mpu.vhdl:108:12:error: multiple assignments for offsets 0:15
rtl/mpu.vhdl:95:12:warning: signal "out_cmd" is never assigned and has no default value
rtl/mpu.vhdl:96:12:warning: signal "out_data" is never assigned and has no default value
eine
@eine
Those seem quite standard when writing VHDL for synthesis.
Julien FAUCHER
@suzizecat
(then a GHDL bug occured message which I may post if it's of any actual use on the current developement stage)
eine
@eine
The latch is likely to be because of some missing else when trying to infer a register.

(then a GHDL bug occured message which I may post if it's of any actual use on the current developement stage)

Yes, please.

Julien FAUCHER
@suzizecat
On an issue or directly here ? (I mean, I don't have much to say beside "I tried and it crashed" and I don't really have a mwe)
eine
@eine
Regarding multiple assignments, I think there might be issues when you assign some bits of a vector in a process and others in a different process, even though there is no conflict. GHDL might assume that both are driving the same signal, while other tools treat them as separate subsignals.
Julien FAUCHER
@suzizecat
I got the latch one, I made something really dirty x)
eine
@eine
For the unassigned ports or signals, that's straightforward :D
Julien FAUCHER
@suzizecat
Well sure x)
Oh, i understand the latch
eine
@eine

On an issue or directly here ? (I mean, I don't have much to say beside "I tried and it crashed" and I don't really have a mwe)

If you don't have a MWE, but you have some repo on GitHub, that's useful too. Many of the projects in #974 have been tested directly.

Julien FAUCHER
@suzizecat
Well, I can push that on a repo
Oh, the multiple assignments will actually be tricky...
Is the synthesis supporting bidirectional ports ?
eine
@eine
The point is, is your device supporting it?
Julien FAUCHER
@suzizecat
Well, that's why I wanted to try is on a FPGA in the first place x)
eine
@eine
I believe that bidirectional ports are supported for I/O (top-level ports). But you cannot use bidirectional signals in modern FPGAs.
Well, some tools might accept them, but they are synthesized as mux-based logic.
Julien FAUCHER
@suzizecat
That's how I though them (and saw that somewhere on internet)
GlenNicholls
@GlenNicholls

I believe that bidirectional ports are supported for I/O (top-level ports). But you cannot use bidirectional signals in modern FPGAs.

You can use bi-directional ports, at least all the modern FPGAs (KU+, Stratix, etc) I've used. But, there is a caveat. Not only does it turn into a mux, but you have to be extremely careful about multi-driven ports. If you aren't you get errors during implementation that lead you a stray

That is, internally there are no tristate buffers. they are present on the IO though
eine
@eine
@GlenNicholls, correct. I mean in a physical sense. The final mapping is not going to be a bidirectional cable.
Julien FAUCHER
@suzizecat
I used a rw_cache_data <= (others => 'Z'); then when I need to write, I have a signal to block the other side from writing and just write my value.
I should definitely change that for a regular I/O system, tho