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  • 15:45
    DanielG commented #2344
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  • Feb 06 22:36
    JimLewis opened #2346
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    [Dependabot]: Bump pyvhdlmodel … (compare)

  • Feb 06 19:15
    dependabot[bot] opened #2345
  • Feb 06 15:20
    DanielG opened #2344
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  • Feb 06 08:40
    tgingold commented #2337
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tgingold
@tgingold
You should use a text file if you want to read a file generated by a tool.
Unai Martinez-Corral
@umarcor
@tgingold, my understanding is that @vblanco20-1 grabs a binary file (.bin, .hex) and it generates a VHDL source file, with the content hardcoded. He is not reading the binary file from VHDL. That's a different use case, the one @HendrikMennen asked about.
tgingold
@tgingold
You're right. Sorry for the confusion!
vblanco20-1
@vblanco20-1
thats indeed what im doing
in case you are interested
nobodywasishere
@nobodywasishere:eowyn.net
[m]
@HendrikMennen: what file are you reading?
nobodywasishere
@nobodywasishere:eowyn.net
[m]
I ran into issues when reading a file if I read the last line, i.e. no newline at the end of the file.
Hendrik Mennen
@HendrikMennen
@nobodywasishere:eowyn.net it is a .bmp file used for image processing
Unai Martinez-Corral
@umarcor
@HendrikMennen see ghdl/ghdl#1758. As Tristan said, binary file formats are implementation dependent.
Therefore, you might need to read the BMP file in VHDL byte by byte.
Alternatively, you might want to have a look at co-simulation examples. My main motivation for using co-simulation is passing images/video/cubes between VHDL and C/Python.
That is, I use C/Python for reading/writing BMP, PNG, TIFF, any other image format; instead of writing those functions in VHDL.
Michael Jørgensen
@MJoergen
I use a tool like xxd to convert a binary file to ASCII, and then use hread() to read it in VHDL.
eine
@eine
As a matter of fact, I wanted to gather multiple examples about dealing with files (text, binary, CSV, hexdumps, etc.) in VHDL >=2008. However, I don't know where to put that content. I feel it doesn't fit in the GHDL docs, nor in the ghdl-cosim docs, or in OSVB... And currently I cannot handle maintaining yet another repo...
nobodywasishere
@nobodywasishere:eowyn.net
[m]
VHDLref? ;)
eine
@eine
Might be :wink:
Ed Bordin
@edbordin
So, I finally got around to looking into why the fpga-toolchain builds were failing and I think it's because GNAT_LARGS was removed from Makefile.in due to being unused :/
I was calling make with GNAT_BARGS="-bargs -E -static" GNAT_LARGS="-static -lz" to force a static link with zlib, is there a better way to do it? Perhaps I should just open a GH issue
in the meantime I might just patch it back in to get things building again
tgingold
@tgingold
GNAT_BARGS still exists, but GNAT_LARGS has been replaced by LDFLAGS.
Ed Bordin
@edbordin
LDFLAGS didn't seem to quite behave the same
the linker flags I'm adding are very sensitive to ordering though because I'm adding -static so I was possibly never using it as intended
tgingold
@tgingold
Do not hesitate to propose a change!
Ed Bordin
@edbordin
I've run out of time today but yes, I agree I should collaborate with you rather than patching downstream!
it doesn't help that I don't really understand all the details of gnatlink etc.
xiretza
@xiretza:xiretza.xyz
[m]
@edbordin: that one's on me, sorry about that, we could just revert that commit
or add a generic GNAT_FLAGS variable
Unai Martinez-Corral
@umarcor
I will rebase ghdl/ghdl#1547, so we can use it as a reference for the windows builds. That covers all the working and non-working setups I could gather.
tgingold
@tgingold
@edbordin For gnatlink, just use -v so that it displays how gcc is called. Then you need to narrow down which command is not correct and what would be the best order for the options.
Ed Bordin
@edbordin
It looks like the fpga-toolchain static builds will soon be superseded by ones managed by yosyshq, so I might just leave it as-is
(I knew this was happening but wasn't sure what the timeline was)
@xiretza:xiretza.xyz yeah that's basically what I ended up doing with a patch, works fine for now. If nobody else is using that flag it probably doesn't need to be reverted
T. Meissner
@tmeissner
Not so cool - GHDL is not included.
T. Meissner
@tmeissner
Time for PRs :smile:
Ed Bordin
@edbordin
they're working on it I think, it's just complicated because it's all cross-compiled from linux
T. Meissner
@tmeissner
Ah, cool :smiley:
Unai Martinez-Corral
@umarcor
I really hope the fpga-toolchain is kept until the oss-cad-suite is improved. Currently, they are reinventing appimage/flatpak manually...
There is 1GB of Ubuntu system libs included in the tarball, and all the executables are wrapped in bash/perl scripts for overriding the linker and library paths.
Martin
@hackfin
Oh my god. Sounds like the Xilinx method.
Unai Martinez-Corral
@umarcor
It is...
Martin
@hackfin
Well, someone will go and dockerize it, eventually.
Unai Martinez-Corral
@umarcor
Most of the tools are dockerised already...
So, fpga-toolchain makes sense because it's a different (all static) solution.
In oss-cad-suite, they are partially duplicating the MINGW packages and they are partially duplicating the hdl/containers.
See YosysHQ/oss-cad-suite-build#1.
Nonetheless, if they want to provide "their own solution for their clients" it makes sense for them to have a branded bundle.
Unai Martinez-Corral
@umarcor
I was about to ask something in the gitter channel of another open source community and I saw they moved to https://zulip.com a week ago.
I didn't know about that software/service.
It looks really nice. It's open source. The default free plan is limited to 10k messages of search history and 5GB of storage. However, they provide the standard plan for open source projects: https://zulip.com/for/open-source/.