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  • 08:02
    tgingold closed #1514
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vblanco20-1
@vblanco20-1
what was the original thinking of using something like Ada for a compiler?
generally every use case ive ever seen of Ada was for things microcontroller/robot related
vblanco20-1
@vblanco20-1
on my end GHDL is the absolute first time ive seen Ada used for something like a compiler
Unai Martinez-Corral
@umarcor

what was the original thinking of using something like Ada for a compiler?

Tristan worked with Ada (at AdaCore). He is an expert in the language.
Other than that, VHDL was based on Ada. Therefore syntax and certain semantics are very similar.
The idea is that VHDL designers can read Ada. That is true. However, the actual problem is that hardware designers can hardly contribute to GHDL because it is compiler, not because of the language. We are lacking knowledge about the complexity of the tool (and the LRM). I don't think using Ada is the main stopper.

OTOH, since GHDL was started 20 years ago, the language ecosystem changed a lot.
Ada tooling feels dated compared to Python, Rust, Golang.
Yet, that's not a problem with Ada only, but also with C/C++.
I believe it's arguable whether GHDL would be better written in C. I think that's what it should be compared. Comparing Ada and Rust is unfair because Rust did not exist for 15 of the last 20 years.
Anyway, we have discussed about "rewritting GHDL in Rust" several times in the last 2-3 years. I believe it might happen at some point.
For it to be true, tho, there needs to be more momentum than around Ada.
So, please, see the rust branch, ask about it, try to understand why Tristan did not switch to Rust yet, even though it has been discussed so much.
Unai Martinez-Corral
@umarcor

ive thought of making my own HDL on top of vhdl

Please, don't call that HDL. None of us is more clever than all the people working on standardising HDL languages during the last 40 years. You will likely design a subset of a subset of an HDL which will need between 5-10y to be barely usable for any real-world application, and not just the very limited subset of use cases you need it for.
Chisel, SpinalHDL, migen, nmigen, Clash, BlueSpec, Silice, myhdl, TL-Verilog... all those are domain specific languages, most of them focused on a very specific topic (writting RISCV microarchitectures). Twice as many were created in the last decade and are absolutely dead.
We do have a problem with open source tooling for HDL. However, reinventing languages will only delay improving the tooling a decade, at least.
Writting tooling for VHDL and/or System Verilog is precisely complex and challenging because they cover lots of use cases which other languages decided to ignore for the sake of simplicity.

Kaleb Barrett
@ktbarrett
@umarcor I learned Rust a couple years ago and tried it out on some random toy projects. After fighting the borrow checker a couple times I stopped and never used it again.
2 replies
Unai Martinez-Corral
@umarcor
You want to write a DSP library? A SoC integration tool? An interface/interconnect management solution? All of those are so interesting, and you can use a DSL for that. You can write the DSL in any software language you want. All of that is absolutely perfect and desirable. Just, please, don't say/think that is an HDL.
vblanco20-1
@vblanco20-1
going from ada to rust makes a lot of sense
safety first language into safety first language
plus rust in general has a very nice ecosystem for compiler related things
Unai Martinez-Corral
@umarcor
I believe that's the main reason for Tristan to consider Rust seriously, while C/C++ do not add much value and the effort is probably not worth it. Just for curiosity, Kaleb, Victor, would feel comfortable with C++? I know you both know it, but I don't know if enough for actually writting a compiler with it.
vblanco20-1
@vblanco20-1
ive been coding cpp for near a decade professionally. I wouldnt really use it for a new copiler written today
Unai Martinez-Corral
@umarcor
Note that the ghdl to yosys plugin is currently done in C++. Also, combining GHDL with Verilator or writting a ghdlator/vhdlator might require C++. There is also UHDM, C++ too.
Kaleb Barrett
@ktbarrett
I am comfortable enough with C++ to use it for just about anything.
T. Meissner
@tmeissner
Isn't the SW-design of a project or the knowledge of it the real "blocker"?
vblanco20-1
@vblanco20-1
string handling is still quite a mess. The standard library uses std::string, but that one has some massive issues regarding the api
T. Meissner
@tmeissner
I also don't used Ada that much before and contributed to GHDL
vblanco20-1
@vblanco20-1
in cpp17 they added stringview, but they dropped it and near everything else in std string and similar still just creates more strings
in almost every cpp project the number 1 blocker is std string doing millions of allocations. Would be worse on a compiler unless the developers are incredibly careful
common things in cpp like splitting a string according to a delimiter will allocate 2 (or more) strings, plus the allocation for the std::vector to holds the string segments
in rust that is a lazy iterator that does 0 allocs. Part of the standard. Checked by the borrowcheck at compile stage to see you arent dangling references
Unai Martinez-Corral
@umarcor
There is also ghdl/ghdl-yosys-plugin#122 for verilog to vhdl conversion, also C++.
@tmeissner, as you see, I'm trying to provide alternatives which allow them to get familiar with the internals of GHDL indirectly. That is, exposing the internals through an API rather than actually modifying the core.
I agree that the language is not a problem in fact.
It's the lack of tooling in the language.
T. Meissner
@tmeissner
I'm not sure which tool is needed in addition to gnat?
A package manager?
Unai Martinez-Corral
@umarcor
Rust/Golang, even Python, have built in documentation generation, style checking, graphviz of the hierarchies/calls, etc.
In GHDL/Ada we have https://ghdl.github.io/ghdl/gnatdoc/. That's just useful for saying that "there is something", not more.
Packaging is interesting too, but that's kind of fundamentally broken in Python and golang, and the ecosystems are still alive.
Packaging is not very useful nowadays, since we have git and system packagers.
m-kru
@m-kru
This topic keeps returning like a boomerang.
Chips4Makers
@fatsiefs:matrix.org
[m]
Chisel, SpinalHDL, migen, nmigen, Clash, BlueSpec, Silice, myhdl, TL-Verilog... all those are domain specific languages, most of them focused on a very specific topic (writting RISCV microarchitectures).
@umarcor: In what way are Chisel, SpinalHDL, migen, nmigen, etc domain specific ? I myself know nmigen well and would claim it is more general than VHDL.
Unai Martinez-Corral
@umarcor

@fatsiefs:matrix.org I don't mean they are necessarily designed to be domain specific in the long term, but I meant they are mostly used as such.

  • Chisel was originally single-clock-domain and could not handle async descriptions. I think that multiple clock domains are supported since v3? Not sure about async.
  • SpinalHDL is mostly used for composing SoCs, mainly around the very successful VexRiscv, Murax, Briey, etc. The language itself can be used for "any" design, and people are writing peripherals for the RISC-V SoCs using those. However, I didn't see any project using SpinalHDL for hardware not part of a RISC-V SoC.
  • Migen (and Litex) are very used for composing SoCs too. It's possible to write hardware with them, but most of the designs I see do integrate HDL cores and use those for building the SoC.

AFAIK, those generate Verilog. SpinalHDL can generate VHDL too, but it's not the default in most of the available designs, hence tweaks are required.

nmigen, I acknowledge it's probably the most different from all of these. whitequark has a very interesting understanding of technology and that's a breakthrough. In this case, the problem I see is the ecosystem. While other languages can explicitly interact with traditional vendor tools, nmigen has been very tightly coupled to Yosys and CXXRTL. Together with the almost absolute lack of documentation, that made it not appealing to people needing an stable solution for the next decades. From a VHDL user perspective, I cannot use nmigen together with VHDL designs and have them simulated without converting the VHDL to something else.

However, if any of these languages might seriously replace VHDL or Verilog in the future, I think nmigen might be the strongest candidate. Moreover, whitequark acknowledged that nmigen and CXXRTL share concepts with VHDL (maybe more than with Verilog, 'cause maybe nmigen is fixing the problems with the Verilog language which do not exist in VHDL because they were solved years/decades ago). From this point of view, I would love nmigen to become "VHDL with Python syntax", not a Python HDL, but THE Python VHDL.

Anyway, my claim is that none of these projects is a valid candidate for the industry in less than 5-10 years of development. All of those languages are 5-10 years old, and now is when we can start talking about them as serious solutions. I was not criticising bluntly, I was just stating that hardware development is hard, very regardless of how clever you are or the languages you use. System Verilog or VHDL are not "better" per se, they just have been worked on for 6x longer.

Unai Martinez-Corral
@umarcor
Although you didn't mention it explicitly, the history of BlueSpec is really interesting. From a System Verilog dialect, to a company around a language, to providing a RISC-V SoC generator, to open sourcing everything.
BTW, does anyone have examples about arbitrary fixed-point arithmetics with nmigen (equivalent to Matlab's fixed-point toolbox or to VHDL 2008's generic packages)?
Kaleb Barrett
@ktbarrett
How do you turn on VHPI tracing in GHDL? I see in the source there is Flag_Trace, but I'm not sure what turns it on/off.
Chips4Makers
@fatsiefs:matrix.org
[m]
@umarcor: I disagree on the 5-10 year timeframe for nmigen usability. I have used VHDL code in nmigen design, used cocotb with modelsim (proprietary I know) for mixed-signal sim. But I agree this is own development not general available. And with GHDL you can only simulate VHDL.
I would rather nmigen not be VHDL with a python syntax as I prefer the implementation of clock domain and synchronous logic over the VHDL one. Maybe you are more interested in MyHDL then as I see that as a reimplementation of VHDL/Verilog mistakes in python 🙂
Kaleb Barrett
@ktbarrett
@umarcor You would compare nMigen to VHDL? I think they pretty different in approach. nMigen is a Python metaprogramming framework on top of a functional RTL-oriented DSL. VHDL is a more traditional simulation language.
tgingold
@tgingold
@ktbarrett --vhpi-trace
Kaleb Barrett
@ktbarrett
@tgingold thanks. I'll add that to the docs.