Chisel, SpinalHDL, migen, nmigen, Clash, BlueSpec, Silice, myhdl, TL-Verilog... all those are domain specific languages, most of them focused on a very specific topic (writting RISCV microarchitectures).
@fatsiefs:matrix.org I don't mean they are necessarily designed to be domain specific in the long term, but I meant they are mostly used as such.
AFAIK, those generate Verilog. SpinalHDL can generate VHDL too, but it's not the default in most of the available designs, hence tweaks are required.
nmigen, I acknowledge it's probably the most different from all of these. whitequark has a very interesting understanding of technology and that's a breakthrough. In this case, the problem I see is the ecosystem. While other languages can explicitly interact with traditional vendor tools, nmigen has been very tightly coupled to Yosys and CXXRTL. Together with the almost absolute lack of documentation, that made it not appealing to people needing an stable solution for the next decades. From a VHDL user perspective, I cannot use nmigen together with VHDL designs and have them simulated without converting the VHDL to something else.
However, if any of these languages might seriously replace VHDL or Verilog in the future, I think nmigen might be the strongest candidate. Moreover, whitequark acknowledged that nmigen and CXXRTL share concepts with VHDL (maybe more than with Verilog, 'cause maybe nmigen is fixing the problems with the Verilog language which do not exist in VHDL because they were solved years/decades ago). From this point of view, I would love nmigen to become "VHDL with Python syntax", not a Python HDL, but THE Python VHDL.
Anyway, my claim is that none of these projects is a valid candidate for the industry in less than 5-10 years of development. All of those languages are 5-10 years old, and now is when we can start talking about them as serious solutions. I was not criticising bluntly, I was just stating that hardware development is hard, very regardless of how clever you are or the languages you use. System Verilog or VHDL are not "better" per se, they just have been worked on for 6x longer.