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  • Jul 30 19:54
    tgingold commented #1827
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vblanco20-1
@vblanco20-1
in almost every cpp project the number 1 blocker is std string doing millions of allocations. Would be worse on a compiler unless the developers are incredibly careful
common things in cpp like splitting a string according to a delimiter will allocate 2 (or more) strings, plus the allocation for the std::vector to holds the string segments
in rust that is a lazy iterator that does 0 allocs. Part of the standard. Checked by the borrowcheck at compile stage to see you arent dangling references
Unai Martinez-Corral
@umarcor
There is also ghdl/ghdl-yosys-plugin#122 for verilog to vhdl conversion, also C++.
@tmeissner, as you see, I'm trying to provide alternatives which allow them to get familiar with the internals of GHDL indirectly. That is, exposing the internals through an API rather than actually modifying the core.
I agree that the language is not a problem in fact.
It's the lack of tooling in the language.
T. Meissner
@tmeissner
I'm not sure which tool is needed in addition to gnat?
A package manager?
Unai Martinez-Corral
@umarcor
Rust/Golang, even Python, have built in documentation generation, style checking, graphviz of the hierarchies/calls, etc.
In GHDL/Ada we have https://ghdl.github.io/ghdl/gnatdoc/. That's just useful for saying that "there is something", not more.
Packaging is interesting too, but that's kind of fundamentally broken in Python and golang, and the ecosystems are still alive.
Packaging is not very useful nowadays, since we have git and system packagers.
m-kru
@m-kru
This topic keeps returning like a boomerang.
Chips4Makers
@fatsiefs:matrix.org
[m]
Chisel, SpinalHDL, migen, nmigen, Clash, BlueSpec, Silice, myhdl, TL-Verilog... all those are domain specific languages, most of them focused on a very specific topic (writting RISCV microarchitectures).
@umarcor: In what way are Chisel, SpinalHDL, migen, nmigen, etc domain specific ? I myself know nmigen well and would claim it is more general than VHDL.
Unai Martinez-Corral
@umarcor

@fatsiefs:matrix.org I don't mean they are necessarily designed to be domain specific in the long term, but I meant they are mostly used as such.

  • Chisel was originally single-clock-domain and could not handle async descriptions. I think that multiple clock domains are supported since v3? Not sure about async.
  • SpinalHDL is mostly used for composing SoCs, mainly around the very successful VexRiscv, Murax, Briey, etc. The language itself can be used for "any" design, and people are writing peripherals for the RISC-V SoCs using those. However, I didn't see any project using SpinalHDL for hardware not part of a RISC-V SoC.
  • Migen (and Litex) are very used for composing SoCs too. It's possible to write hardware with them, but most of the designs I see do integrate HDL cores and use those for building the SoC.

AFAIK, those generate Verilog. SpinalHDL can generate VHDL too, but it's not the default in most of the available designs, hence tweaks are required.

nmigen, I acknowledge it's probably the most different from all of these. whitequark has a very interesting understanding of technology and that's a breakthrough. In this case, the problem I see is the ecosystem. While other languages can explicitly interact with traditional vendor tools, nmigen has been very tightly coupled to Yosys and CXXRTL. Together with the almost absolute lack of documentation, that made it not appealing to people needing an stable solution for the next decades. From a VHDL user perspective, I cannot use nmigen together with VHDL designs and have them simulated without converting the VHDL to something else.

However, if any of these languages might seriously replace VHDL or Verilog in the future, I think nmigen might be the strongest candidate. Moreover, whitequark acknowledged that nmigen and CXXRTL share concepts with VHDL (maybe more than with Verilog, 'cause maybe nmigen is fixing the problems with the Verilog language which do not exist in VHDL because they were solved years/decades ago). From this point of view, I would love nmigen to become "VHDL with Python syntax", not a Python HDL, but THE Python VHDL.

Anyway, my claim is that none of these projects is a valid candidate for the industry in less than 5-10 years of development. All of those languages are 5-10 years old, and now is when we can start talking about them as serious solutions. I was not criticising bluntly, I was just stating that hardware development is hard, very regardless of how clever you are or the languages you use. System Verilog or VHDL are not "better" per se, they just have been worked on for 6x longer.

Unai Martinez-Corral
@umarcor
Although you didn't mention it explicitly, the history of BlueSpec is really interesting. From a System Verilog dialect, to a company around a language, to providing a RISC-V SoC generator, to open sourcing everything.
BTW, does anyone have examples about arbitrary fixed-point arithmetics with nmigen (equivalent to Matlab's fixed-point toolbox or to VHDL 2008's generic packages)?
Kaleb Barrett
@ktbarrett
How do you turn on VHPI tracing in GHDL? I see in the source there is Flag_Trace, but I'm not sure what turns it on/off.
Chips4Makers
@fatsiefs:matrix.org
[m]
@umarcor: I disagree on the 5-10 year timeframe for nmigen usability. I have used VHDL code in nmigen design, used cocotb with modelsim (proprietary I know) for mixed-signal sim. But I agree this is own development not general available. And with GHDL you can only simulate VHDL.
I would rather nmigen not be VHDL with a python syntax as I prefer the implementation of clock domain and synchronous logic over the VHDL one. Maybe you are more interested in MyHDL then as I see that as a reimplementation of VHDL/Verilog mistakes in python 🙂
Kaleb Barrett
@ktbarrett
@umarcor You would compare nMigen to VHDL? I think they pretty different in approach. nMigen is a Python metaprogramming framework on top of a functional RTL-oriented DSL. VHDL is a more traditional simulation language.
tgingold
@tgingold
@ktbarrett --vhpi-trace
Kaleb Barrett
@ktbarrett
@tgingold thanks. I'll add that to the docs.
Martin
@hackfin
@umarcor there are mature FP toolboxes for MyHDL I know of. But isn't this a bit off topic?
vblanco20-1
@vblanco20-1
Maybe you know about it. Ive been using a Basys3 board as its the university one, but im continuing development past university and need to get a new FPGA. Ive been thinking of the board that the MisTER project uses, which is a DE-10 Nano (intel). How is the ecosystem with that vs the xilinx based stuff of the basys3?
for the goal of creating a full reimplementation of a gameboy and other cpu-related projects
vblanco20-1
@vblanco20-1
the actual fpga is Artix7 (basys3) vs Cyclone5(Nano)
Kaleb Barrett
@ktbarrett
@vblanco20-1 By CPU projects do you mean softcore or SoC? A Zybo board would work if you want to stay in the Xilinx ecosystem. It's what we used in my undergrad (after upgrading from Nexys 3's) It has roughly the same amount of PL as the basys3 + an ARM processor. There are PMOD adapters for VGA. Oh there is a discount if you still have your .edu address.
vblanco20-1
@vblanco20-1
more about creating cpus
the de10nano is used in the mister project which is something i could contribute to or have fun tinkering with
absolute best would be an Analogue Pocket but seems those will be impossible to fund
portable fpga in the shape of a gameboy with fun features and stuff
Julian Kemmerer
@JulianKemmerer
Hi folks couldn't help but see yall were talking about alternative HDLs, comparing the 'domain specificness' of them - which i definitely hear the 'generate me a SoC' bias in some of those
And then of course that generating vhdl from these tools
So i just wanted to point everyone to yet another tool , PipelineC, generates vhdl and works with ghdl yosys next pnr flow https://github.com/JulianKemmerer/PipelineC/wiki
vblanco20-1
@vblanco20-1
@JulianKemmerer HLS?
well not so high level
that actually looks great,
like exactly what i would like for my project
Julian Kemmerer
@JulianKemmerer
Hey thanks eh - you can do hdl style or hls auto pipeline style , combine the two
More than happy to help you get going on something
@vblanco20-1
Unai Martinez-Corral
@umarcor

I disagree on the 5-10 year timeframe for nmigen usability. I have used VHDL code in nmigen design, used cocotb with modelsim (proprietary I know) for mixed-signal sim. But I agree this is own development not general available.

@fatsiefs:matrix.org I meant 5-10y since someone decides to (re)invent a language, not from now onward. nmigen has been 3y in development after 10y of migen and +10y of myHDL. It didn't come out of nowhere.
By the same token, 3y ago cocotb was dead, after a very successful start. FOSSi, Kaleb and others spent the last 2 years working so hard, and they still have at least 1y of development for starting to consider it mature.
Note that my reply was targeted at a person that suggested he would write his own HDL from scratch. I suggested him to better build on any of those existing projects/languages precisely so those can get to maturity faster.

You would compare nMigen to VHDL? I think they pretty different in approach. nMigen is a Python metaprogramming framework on top of a functional RTL-oriented DSL. VHDL is a more traditional simulation language.

@ktbarret, could you please elaborate? I'm thinking about a user who needs to learn both hardware design and a language for hardware description at the same time, as a tool for them to use in the following 1-2 decades. I don't think whether the implementation is a metaprogramming language or a traditional language is relevant. It's about what they can express and what they cannot. Entities/architectures/modules/components/bodies, structs/records/interfaces, FFs/memories, boolean logic/muxes, fixed-point and floating-point DSP...

there are mature FP toolboxes for MyHDL I know of. But isn't this a bit off topic?

@hackfin, would mind providing any reference?

We can continue in hdl/community, if you prefer.

Ive been thinking of the board that the MisTER project uses, which is a DE-10 Nano (intel). How is the ecosystem with that vs the xilinx based stuff of the basys3

@vblanco20-1 I suggest you ask in the symbiflow channel in IRC, and/or in project mistral. Support for intel/altera devices is less advanced than Lattice or Xilinx. For Xilinx, there are two PnR tools, nextpnr and VTR. For Intel, I think they are working with nextpnr only.

I would recommend an ECP5 device and a board with an Artix.

I would stay away from Zynq, unless you have any actual usage for the single or dual ARM cores. You cannot use the PL without understanding and initialising the PS.
I have a PYNQ-Z1 and some Arty, and there is no advantage in the first one for RTL only designs. However, Zynq is very interesting if you want to run Linux on ARM and accelerate things in the FPGA.

the de10nano is used in the mister project which is something i could contribute to or have fun tinkering with

I believe that the mister project might greatly benefit from being ported/adapted to an open board based on one of the largest ECP5. However, mister seems to be not only the FPGA board, but a whole stack of boards...

vblanco20-1
@vblanco20-1
the boards are basically addons
the main thing is on the de-10 nano, but the extras are to give it extra ram, more usb ports, and analog output (VGA)
Kaleb Barrett
@ktbarrett
@marlonjames Thanks. I figured those options would be with the other trace options in the debug section, which is what confused me.
Unai Martinez-Corral
@umarcor

the main thing is on the de-10 nano, but the extras are to give it extra ram, more usb ports, and analog output (VGA)

@vblanco20-1 With some ECP5 or Artix boards you would have some of those extras. For instance https://shop.lambdaconcept.com/home/46-2-ecpix-5.html#/2-ecpix_5_fpga-ecpix_5_85f, as direct alternative to Arty/Zybo.