Yes, but my point is that the warning I want to backtrace is at simulation time
I think that using the warn arguments for analysis and elaboration is not limited to those stages. You are telling GHDL that you want those features enabled.
Repost from @LarsAsplund
Let's see if we can have a LinkedIn survey with any statistical significance https://www.linkedin.com/posts/plc2-gmbh_vhdl-osvvm-fpga-ugcPost-6817744189200076800-OUeX
Open Source VHDL Design Explorer (OSVDE) is a PoC for showcasing the capabilities of the abstract language model provided by pyVHDLModel and pyGHDL. It's a tkinter GUI for exploring VHDL repos/projects.
Kudos to @Paebbels and Tristan Gingold! :heart_eyes:
ghdl-dom pretty -f FILENAME.vhdon all the sources of GHDL, OSVVM, UVVM, VUnit, PoC, microwatt and NEORV32. In the "Captured stdout call" you can see the identifiers that were properly parsed and printed.