ghdl/Lobby

eine

@eine

Yes, but my point is that the warning I want to backtrace is at simulation time

I think that using the warn arguments for analysis and elaboration is not limited to those stages. You are telling GHDL that you want those features enabled.

Julien FAUCHER

@suzizecat

Oooh

I’ll test it out, then

eine

@eine

The point is that you cannot decide it at runtime. You need to decide it previously.

As @cmarqu and @ktbarrett, do not be mislead by the Makefile plumbing in cocotb. That is helpful for some users but misleading for others. Try to understand the stages:

Build a shared lib with cocotb's VPI or VHPI interface
pass it to GHDL
Start the simulation with GHDL in charge
Let GHDL call the vpi (shared lib) which loads Python and cocotb internally
cocotb sets the callbacks by interpreting Python and passing arguments to the shared library
GHDL goes forward and executes the callbacks when necessary (which go back to the Python definitions)

This is the equivalent using VUnit: https://github.com/umarcor/osvb/blob/main/SFF/test/run.py#L18-L29

Julien FAUCHER

@suzizecat

Indeed, my issue wasn’t with cocotb, but rather with the possibility of using --warn-error at simulation time

eine

@eine

The point is that you need to understand how do cocotb makefiles allow you to pass the arguments at analysis/elaboration time.

It's not cocotb itself, but the plumbing.

Julien FAUCHER

@suzizecat

Indeed, but no point trying to figure it out if GHDL doesn’t allows it altogether :wink:

Patrick Lehmann

@Paebbels

Repost from @LarsAsplund

Let's see if we can have a LinkedIn survey with any statistical significance https://www.linkedin.com/posts/plc2-gmbh_vhdl-osvvm-fpga-ugcPost-6817744189200076800-OUeX

Patrick Lehmann

@Paebbels

Maybe you want to give a :thumbsup: or comment when you use GHDL with CI: https://www.linkedin.com/posts/plc2-gmbh_vivado-riviera-plc2-activity-6818806650049183744-71oY

Martin

@hackfin

I don't do linkedin, but GHDL has been used for CI/verification here for a quite a few complex projects (JPEG encoder SoC). Back then nobody took interest though. Always: thumbs up.

Unai Martinez-Corral

@umarcor

@tgingold, it is theoretically possible to call a foreign function from VHDL for synthesis, isn't it?

The use case is, e.g., generating some values to be used in the generic map of a PLL instantiation. icestorm and prjtrellis provide icepll and ecppll, respectively.
So, I'm thinking about wrapping the call to those tools as VHPIDIRECT functions which returns an struct (record) with the parameters for the instantiation.

I know that top-level generics or code-generation of packages is the most used solution. But I wonder if reusable utilities provided as a VHDL package can help keeping the complexity local.

Unai Martinez-Corral

@umarcor

https://twitter.com/unaimarcor/status/1415928619659145216

Open Source VHDL Design Explorer (OSVDE) is a PoC for showcasing the capabilities of the abstract language model provided by pyVHDLModel and pyGHDL. It's a tkinter GUI for exploring VHDL repos/projects.
Kudos to @Paebbels and Tristan Gingold! :heart_eyes:
See https://umarcor.github.io/osvb/apis/project.html#open-source-vhdl-design-explorer-osvde

Carlos Alberto Ruiz Naranjo

@qarlosalberto

really nice! <3

tgingold

@tgingold

@umarcor Yes it is, but I am not sure it is currently supported.

Unai Martinez-Corral

@umarcor

:thumbsup:

svenn71

@svenn71

why is it an error if yosys-ghdl-plugin infers a latch during synth in yosys?

I am trying to teach qflow some vhdl, so I translated the benchmark map9v3.v to vhdl with iverilog -tvhdl unmodified

xiretza

@xiretza:xiretza.xyz

[m]

see ghdl/ghdl#938

svenn71

@svenn71

thanks a lot. should I punish myself for not searching the issues before asking?

eine

@eine

We don't enforce people damaging themselves for spurious reasons :tongue:

svenn71

@svenn71

I now got motivated by the quick response to my question and will refrain from using internet search in the future

eine

@eine

Overall, this is a very low traffic room, so as long as you don't abuse I personally like direct human interaction from time to time :smile:

Julien FAUCHER

@suzizecat

I might have asked this before but, is GHDL able to output an indexer-like output ? (some kind of list of all identifiers in the code with their position and the fact that an identifier in a given place is a definition or a reference)

Julien FAUCHER

@suzizecat

(I just saw pyGHDL which should be my lifesaver here)

Just a note about the language server, you might not know about and be interested in pygls which is great to build language server based upon LSP

Unai Martinez-Corral

@umarcor

@suzizecat what are "all identifiers" for you?

absolutely anything? generics, ports, constants, signals, instantiations, processes, blocks, etc.?

pyGHDL.dom is meant for that. The minimal example for printing entities, generics and ports only is https://github.com/vhdl/pyVHDLModel#list-all-entities-with-generics-and-ports

pyVHDLModel will allow to retrieve any identifier, but it is not 100% ready yet. So, the answer to your question depends on how deep you want to dive.

Julien FAUCHER

@suzizecat

@umarcor that would be "as much as possible" . I'm currently working on a system verilog language server that take the Verible indexer output and provide all the go-to definition/references stuff. I would like to get as much identifiers as possible to have a cross-language LS as much exhaustive as possible.

Unai Martinez-Corral

@umarcor

Then, I'm not sure you want to use pyGHDL.dom. Maybe you want to look at pyGHDL.lsp. Both of them use libghdl, but the API is different.

Julien FAUCHER

@suzizecat

I'll have a look, thanks !

Unai Martinez-Corral

@umarcor

@suzizecat see https://ghdl.github.io/extended-tests/. That is the result of running ghdl-dom pretty -f FILENAME.vhd on all the sources of GHDL, OSVVM, UVVM, VUnit, PoC, microwatt and NEORV32. In the "Captured stdout call" you can see the identifiers that were properly parsed and printed.

As you can see, 98.67% of the sources can be successfully processed, although not all the internal content is converted to the VHDLModel yet.

tgingold

@tgingold

@suzizecat There is ghdl --xref, but it might be to heavy for an lsp.

Unai Martinez-Corral

@umarcor

I'm concerned with some very weird behaviour of GHDL on some containers. Performance is so bad that execution time is increased significantly and CI jobs timeout. That is, tasks which should need 30-60 min require 6+ h!
In NEORV32, workflow 'riscv-arch-test' needs 40-60 min (dependending on parallelisation). If a container is used (umarcor/neorv32@7d2331a) it runs out of time: https://github.com/umarcor/neorv32/actions/runs/1053111918. Note that the problem is only happening with the "I" testsuite. All other suites are executed as expected (actually, faster due to the reduced startup/installation delay).

Tiago Gomes

@tasgomes

Hi everyone, sorry for the long post but I am trying to give as much info as I can.

I am trying to run a Testbench with GHDL but I am having some problems with a Xilinx component.

I am using the versions:

GHDL 1.0.0
Vivado 2020.2
VUnit 4.5.0

FYI my testbench runs fine with Modelsim PE 2020.1.

I compiled the Xilinx libraries using GHDL with the following command:

$(GHDL_PATH)/lib/ghdl/vendors/compile-xilinx-vivado.sh --all --vhdl2008 --source $(VIVADO_PATH)/data/vhdl/src --output $(VENDOR_LIB_RELDIR)/ghdl

So when I run my TB with GHDL I get these errors that the BITSLICE_CONTROL and RX_BITSLICE (xilinx) components are not bound.

The following errors are shown during execution of simulation:

(..)\selectio_sliceA\selectio_sliceA_sim_netlist.vhdl:471:1:warning: instance "\BITSLICE_CTRL[0].bs_ctrl_inst\" of component "bitslice_control" is not bound [-Wbinding]
\BITSLICE_CTRL[0].bs_ctrl_inst\: unisim.vcomponents.BITSLICE_CONTROL
(...)
(...)\selectio_sliceA\selectio_sliceA_sim_netlist.vhdl:1466:1:warning: instance "\RX_BS[0].rx_bitslice_if_bs\" of component "rx_bitslice" is not bound [-Wbinding]
\RX_BS[0].rx_bitslice_if_bs\: unisim.vcomponents.RX_BITSLICE

This means the component is not being bound correctly, i.e. not found in the unisim library.

I checked Modelsim compilation log (.cxl.vhdl.unisim.unisim.nt64.log) and we can see the component RX_BITSLICE is being compiled into the unisim library.

Model Technology ModelSim PE vcom 2020.1 Compiler 2020.01 Jan 28 2020
Start time: 12:59:30 on Jul 21,2021
vcom -source -93 -64 -work unisim -f D:\_build\utec_002\fw\sim\sim_lib\modelsim/unisim/.cxl.vhdl.unisim.unisim.nt64.cmf -f D:\_build\utec_002\fw\sim\sim_lib\modelsim/unisim/.cxl.vhdl.secureip_vhdl_unisim.unisim.nt64.cmf 
-- Loading package STANDARD
(...)
-- Compiling entity RXTX_BITSLICE
-- Compiling architecture RXTX_BITSLICE_V of RXTX_BITSLICE
-- Compiling entity RX_BITSLICE
-- Compiling architecture RX_BITSLICE_V of RX_BITSLICE
(...)

Interesting in the GHDL compiled libraries, the unisim folder contain several object (*.o) files but no RX_BITSLICE is present there:

xxx@yyy MINGW64 (...)/sim/sim_lib/ghdl/unisim/v08
$ ls -l | grep 'RX_BITSLICE'
`

However, if I check the secureip folder, then I can find the RX_BITSLICE component:

xxx@yyy MINGW64 (...)/sim/sim_lib/ghdl/secureip/v08
$ ls -l | grep 'RX_BITSLICE'
-rw-r--r-- 1 xxx 1049089  226109 Jul 22 09:41 RX_BITSLICE.o

Seems to me that GHDL is compiling the RX_BITSLICE into the wrong library, in this case into the secureip instead of unisim.

In my run.py, I am mapping the libraries as follow:

    # Add vendor libraries
    if args.simulator == 'modelsim' :
        vu.add_external_library("unisim", join(args.vendor_lib, "./modelsim/unisim"))
        vu.add_external_library("secureip", join(args.vendor_lib, "./modelsim/secureip"))
    else:
        vu.add_external_library("unisim", join(args.vendor_lib, "./ghdl/unisim/v08"))
        vu.add_external_library("secureip", join(args.vendor_lib, "./ghdl/secureip/v08"))

Does someone has any idea how can I fix this? Thanks in advance.

Patrick Lehmann

@Paebbels

@tasgomes the compilation into secureip/unisim is correct. The problem is, this IP core is encrypted. So either way you can't simulate it with GHDL.
You can try to write your one tiny replacement model to get it's behavior.

Tiago Gomes

@tasgomes

@Paebbels I see. Thanks for the quick reply.

Unai Martinez-Corral

@umarcor

@tasgomes, you can also tell Xilinx about that, either through their forums or "your" distributor. It's unlikely they will ever allow/support GHDL to simulate that IP, however, since they are "driven by customer demands" it's important to let them know what the customers want.

Tiago Gomes

@tasgomes

@umarcor Just did that this morning ;)

Unai Martinez-Corral

@umarcor

:heart_eyes:

GlenNicholls

@GlenNicholls

If you opened an AR, feel free to point us to it so we can give it kudos

I would be ecstatic if Xilinx supported GHDL at some point

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