pranavb-ca on fix_hvx_intrinsics
Merge branch 'master' of https:… Merge branch 'master' of https:… Fix access to Hexagon intrinsic… (compare)
steven-johnson on 4462
abadams on apps_from_autoscheduler
Add BGU implementation Add histogram equalization Add max filter and 4 more (compare)
abadams on define_div_by_zero
Calculate Expr bounds using fun… Added JIT-test and removed appl… Merge branch 'master' of https:… and 65 more (compare)
vksnk on increase-device-num
vksnk on pos_inf-memory-assert
vksnk on master
Check if shared memory allocati… Use has_upper_bound() to check … Merge pull request #4467 from h… (compare)
bin/Demosaic.o', needed bybin/process'. Stop.
Hi All, i was looking at issue 2317 (halide/Halide#2317) where input.dim(0).set_min(0) was resulting in slower code on CPU. Further digging into code and some experiment showed that slowness is only due to input.dim(0).set_min(0) and not due to input.dim(1).set_min(0).
In the codegen, i see some checks and asserts for "halide_buffer_is_bounds_query" and these are inserted on CPU side always. Even if the schedule is offloaded to Hexagon, the asserts are always inserted in CPU code. Hence the slowness is always observed on CPU schedule, but not on Hexagon.
Q - For schedules offloaded to Hexagon, even if the asserts are on CPU side, why isn't slowness observed? I assume we are measuring time which involves the CPU to Hexagon and back offload time too. Any idea?