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  • May 17 20:23
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The current development effort is focused on CLIAbstraction and ToolSetup; however, fine-grained log processing is in the scope.
Unai Martinez-Corral
@umarcor
Patrick Lehmann
@Paebbels
It it possible that installing Quartus 21.1 forgets to install MS VC++ Runtime 12.0?
When calling vsim from command line, it complains about missing MS VC++ Runtime DLLs ...
Tomasz Hemperek
@themperek
Rodrigo A. Melo
@rodrigomelo9
Is related AxREGION, with an example use case. Somebody is suggesting using IDs instead. Ideas/comments will be appreciated :-D
Rodrigo A. Melo
@rodrigomelo9
I have more than one AXI-M that will access one AXI-S. The AXI-S should behave differently based on something (there are several memory banks, which should be addressed in different ways). The first approach is an extra interface to specify the mode, but I want a shortcut (some AXI signaling) to avoid extra latency between petitions.
3 replies
Not sure if REGIONs are the best option and if IDs are one alternative.
Rodrigo A. Melo
@rodrigomelo9
Hi @mithro @olofk . Which is the best link to promote GSoC for tools related to our interest? 🤪 I would like to promote it in Argentina.
Tim 'mithro' Ansell
@mithro
Both the FOSSi Foundation and CHIPS Alliance projects?
Rodrigo A. Melo
@rodrigomelo9
Yes
Karol Gugala
@kgugala
@rodrigomelo9 you can use this list https://github.com/f4pga/ideas/blob/gsoc-2022/gsoc-2022-ideas.md (for tooling projects)
nobodywasishere
@nobodywasishere:eowyn.net
[m]
test test
whole internet crashed for a minute, wanted to see if this still worked
xiretza
@xiretza:xiretza.xyz
[m]
there seems to be some global roughness right now
Rodrigo A. Melo
@rodrigomelo9
Thanks @kgugala I think that I saw something similar from FOSSi, and I know that there is also something related to Teros HDL. Maybe I need to provide links to the generic explanation about GSoC and then, links to the list with ideas for these projects.
Olof Kindgren
@olofk
@rodrigomelo9 TerosHDL is mentoring through FOSSi Foundation. We have some general info here https://www.fossi-foundation.org/gsoc with a link to our project ideas
Rodrigo A. Melo
@rodrigomelo9
Great! Thanks Olof.
Rodrigo A. Melo
@rodrigomelo9
https://www.linkedin.com/posts/rodrigoalejandromelo_google-open-source-blog-activity-6907448383058124801-I5PJ In Spanish, because I want to promote it in the region (South America), where I feel is not a well-known opportunity.
Rodrigo A. Melo
@rodrigomelo9
I feel that it probably exists, but I'm not sure where... I would like to specify an HDL file (VHDL and/or [System]Verilog) and based on its entity/module, generates the instantiation code. I would like to specify the output format (it means, maybe the input is verilog but the output VHDL) and things such as if I want to specify generics/parameters or not (to use the default values only). Could be desirable also to specify the indentation of the resulting code snippet.
Does it exist? If not, I guess I can use Surelog/Verible (not sure which I need to use when) for Verilog and something from the GHDL side (@umarcor) to create my own.
Carlos Alberto Ruiz Naranjo
@qarlosalberto
In command line?
Rodrigo A. Melo
@rodrigomelo9
I :heart: you haha I'm using TerosHDL with VScodium, so it is a great workaround, but I'm more a console guy, so I would like to find the alternative also.
I'm playing with it and is really good, thanks!
Rodrigo A. Melo
@rodrigomelo9
Another topic. I added a cocotb tutorial (and a few very basic examples) into my FOSS-for-FPGA repo https://rodrigomelo9.github.io/FOSS-for-FPGAs/cocotb.html
Tim 'mithro' Ansell
@mithro
People here might find this talk from one of my peers, Chris Leary, interesting -- Recording @ https://www.youtube.com/watch?v=9s1hLc_BoNw - It was given at the LATTE'22 conference and covers a lot of thinking and philosophy about compilers (including silicon compilers) and converting software engineers into hardware engineers.
Tim 'mithro' Ansell
@mithro
Julian Kemmerer
@JulianKemmerer
That was a great LATTE talk from Chris. I love the idea of trying to have hardware and software folks meet in the middle. I know there are plenty of embedded C software folks who could do digital design if given a 'frontend'/mask over the details of RTL
Unai Martinez-Corral
@umarcor

Does it exist? If not, I guess I can use Surelog/Verible (not sure which I need to use when) for Verilog and something from the GHDL side (@umarcor) to create my own.

@rodrigomelo9 see https://github.com/vhdl/pyVHDLModel and https://github.com/edaa-org/pySVModel (edaa-org/pySVModel#11).
https://umarcor.github.io/osvb/apis/project/OSVDE.html shows how to get the generics and ports from pyGHDL.dom.

image.png
Rodrigo A. Melo
@rodrigomelo9
Thanks @umarcor. Yes, I saw pyVHDLModel but nothing is available (yet) under pySVModel
Michael Büchler
@mbuechl:matrix.org
[m]
Hi all! I was looking for something to generate a VHDL wrapper for VHDL entities with custom record types as ports, e.g. 't_axi4_m2s' for an AXI4 interface. The wrapper should expose those as multiple 'std_logic' and 'std_logic_vector' ports, so it can be packaged as Vivado IP. I think building something based on pyVHDLModel might be a good idea here too, similar to Rodrigo's case above - or do you maybe know of anything in existence? I can't be the first to be bothered by this :D
Ben Reynwar
@benreynwar
I needed to do this a while back and wrote slvcodec. The VHDL parsing is based off VUnit's parsing (pyVHDLModel wasn't around yet), and it's probably quite specific to my style of VHDL, but it might be worth checking out.
The flatten_generator.py creates a VHDL wrapper with flattened types.
Michael Büchler
@mbuechl:matrix.org
[m]
Neat!! I was able to use flatten_generator.vhd to get my record-type ports wrapped as individual std_logic/std_logic_vector ports, just what I needed. It doesn't handle multiple levels of record types, does it? I'll try it out more on Monday, and find out how generics are handled. Thanks for sharing!
  • flatten_generator.py of course
Ben Reynwar
@benreynwar
Sweet! I'm glad it worked for you! It should handle multiple levels of arrays and records, but you might run into bugs. I mostly using SystemVerilog at the moment so I don't use it much, but I know my previous employer is still using it.
Tim 'mithro' Ansell
@mithro
GlenNicholls
@GlenNicholls

@mbuechl:matrix.org I have something similar to what you're looking to do that is pure VHDL. I can't find my original reference, but I believe it was adapted from the discussion and links at https://stackoverflow.com/questions/3985694/serialize-vhdl-record. There was a serialize/deserialize repo on GitHub, but I can't find it now.

Essentially, I use a state record to keep track of indexes and use pack/unpack procedures for each standard type to build the to_slv/to_<record type> functions. Below is a simple version for to range:

    procedure pack(
        variable state     : inout pack_state_t;
        variable target    : inout std_ulogic_vector;
        constant push_data : in    std_ulogic_vector
    ) is
        constant length : integer := push_data'length;
    begin
        target(state.idx to state.idx + length-1) := push_data;
        state.idx := state.idx + length;
    end procedure;

    procedure unpack(
        variable state    : inout pack_state_t;
        constant source   : in    std_ulogic_vector;
        variable pop_data : out   std_ulogic_vector
    ) is
        constant length : integer := pop_data'length;
    begin
        pop_data  := source(state.idx to state.idx + length-1);
        state.idx := state.idx + length;
    end procedure;

Then, you can do something like this for your record:

type ex_t is record
    sl     : std_ulogic;
    slv8   : std_ulogic_vector(7 downto 0);
    sint16 : signed(15 downto 0);
end record;
constant SIZE : integer := 25;

-- this packs an SLV where 'left (MSW) is `sl` record element
function to_slv (arg : ex_t) return std_ulogic_vector is
    variable v_ret : std_ulogic_vector(SIZE-1 downto 0);
    variable state : pack_state_t := init_pack_state(target=>v_ret);
begin
    pack(state, v_ret, arg.sl);
    pack(state, v_ret, arg.slv8);
    pack(state, v_ret, arg.sint16);
    return v_ret;
end function;

My state record is slightly more complicated to handle the range, how sub-words are packed, etc. However, the idx just keeps track of the starting index such that I can change the record declaration without having to remember to modify the to_slv function.

The downside with this is there is no way in VHDL (at least with <=2008) to determine a record's size, so I update SIZE when updating the record def. You could probably do something like SIZE = 1+ex_t.slv8'length+... as well to keep it a bit more fool-proof and understandable

2 replies
m-kru
@m-kru
Has anyone ever analyzed GTKWave source code? How would you rate its complexity?
xiretza
@xiretza:xiretza.xyz
[m]
to be quite frank, it's fairly horrifying to look at :/
I bailed the last couple times I thought about touching it
Rob Taylor
@rob_chipflow:matrix.org
[m]
maybe wavedrom would be a better codebase to start from for any wave viewer functionality
Colin Marquardt
@cmarqu
The wavedrom author has https://github.com/wavedrom/zoom
Colin Marquardt
@cmarqu
Tim 'mithro' Ansell
@mithro
@matthewvenn - Just published a walkthrough video showing all the steps needed to get a design ready for submission to the 6th SkyWater Google Shuttle! - https://www.youtube.com/watch?v=MNuoYz_MM-c