hdl/community

@mbuechl:matrix.org I have something similar to what you're looking to do that is pure VHDL. I can't find my original reference, but I believe it was adapted from the discussion and links at https://stackoverflow.com/questions/3985694/serialize-vhdl-record. There was a serialize/deserialize repo on GitHub, but I can't find it now.

Essentially, I use a state record to keep track of indexes and use pack/unpack procedures for each standard type to build the to_slv/to_<record type> functions. Below is a simple version for to range:

    procedure pack(
        variable state     : inout pack_state_t;
        variable target    : inout std_ulogic_vector;
        constant push_data : in    std_ulogic_vector
    ) is
        constant length : integer := push_data'length;
    begin
        target(state.idx to state.idx + length-1) := push_data;
        state.idx := state.idx + length;
    end procedure;

    procedure unpack(
        variable state    : inout pack_state_t;
        constant source   : in    std_ulogic_vector;
        variable pop_data : out   std_ulogic_vector
    ) is
        constant length : integer := pop_data'length;
    begin
        pop_data  := source(state.idx to state.idx + length-1);
        state.idx := state.idx + length;
    end procedure;

Then, you can do something like this for your record:

type ex_t is record
    sl     : std_ulogic;
    slv8   : std_ulogic_vector(7 downto 0);
    sint16 : signed(15 downto 0);
end record;
constant SIZE : integer := 25;

-- this packs an SLV where 'left (MSW) is `sl` record element
function to_slv (arg : ex_t) return std_ulogic_vector is
    variable v_ret : std_ulogic_vector(SIZE-1 downto 0);
    variable state : pack_state_t := init_pack_state(target=>v_ret);
begin
    pack(state, v_ret, arg.sl);
    pack(state, v_ret, arg.slv8);
    pack(state, v_ret, arg.sint16);
    return v_ret;
end function;

My state record is slightly more complicated to handle the range, how sub-words are packed, etc. However, the idx just keeps track of the starting index such that I can change the record declaration without having to remember to modify the to_slv function.

The downside with this is there is no way in VHDL (at least with <=2008) to determine a record's size, so I update SIZE when updating the record def. You could probably do something like SIZE = 1+ex_t.slv8'length+... as well to keep it a bit more fool-proof and understandable