by

Where communities thrive


  • Join over 1.5M+ people
  • Join over 100K+ communities
  • Free without limits
  • Create your own community
People
Activity
  • Jul 02 23:21
    agathver synchronize #370
  • Jul 02 22:57
    agathver commented #460
  • Jul 02 16:25
    kristynfudge commented #460
  • Jul 01 22:51
    agathver commented #460
  • Jul 01 20:31
    kristynfudge opened #460
  • Jun 24 07:34
    ShashankVM edited #459
  • Jun 24 07:33
    ShashankVM edited #459
  • Jun 24 07:30
    ShashankVM commented #459
  • Jun 21 08:23
    ShashankVM closed #459
  • Jun 21 08:23
    ShashankVM commented #459
  • Jun 21 04:26
    ShashankVM edited #459
  • Jun 21 04:25
    ShashankVM edited #459
  • Jun 20 17:25
    ShashankVM edited #459
  • Jun 20 17:22
    ShashankVM edited #459
  • Jun 20 17:18
    ShashankVM edited #459
  • Jun 20 17:17
    ShashankVM edited #459
  • Jun 20 17:16
    ShashankVM opened #459
  • Jun 06 18:10
    dependabot[bot] labeled #458
  • Jun 06 18:10
    dependabot[bot] labeled #458
  • Jun 06 18:10
    dependabot[bot] opened #458
Pankaj Kumar Singh
@pankajthegeek
Hello everyone, my name is Pankaj Kumar. I'm 2nd year student of MCA at NIT Bhopal.
Pankaj Kumar Singh
@pankajthegeek
@imphil could you please let me know if anybody else is working for this.
Pankaj Kumar Singh
@pankajthegeek
Please ignore as due to corona lockdown in India and limited mobile data in the rural area, I will not be applying for GSOC under this project.
Ali-Sed
@Ali-Sed
Hi everyone, I was wondering whether we should just talk about one project in our proposal for GSoC or we can mention a few of them in the file that we're uploading?
Shashank V M
@ShashankVM
@Ali-Sed , you should do only one project in a proposal. You can submit 3 proposals - hence 3 projects.
avinaba123
@avinaba123
@stevehoover Sir have question about the project "TL-Verilog Timing Reports". I just want to know what are the files that will be provided in this project like the verilog file, constrain files, library files, .csv files?
@stevehoover Sir in this project detail it is defined as we have to build scripts to map RTL signal names to their original TL-Verilog names. So there will be some .csv file which will map. Am I right?
Steve Hoover
@stevehoover
@avinaba123 TL-Verilog tools are capable of generating SystemVerilog that defines signals using TL-Verilog naming conventions and hierarchy that are assigned to their Verilog/SystemVerilog counterparts. This can be used, or tools can be modified to produce CSV or similar mappings. I don't think there's much complexity to this project; it's mostly parsing of the output of various synthesis tools. But there is the matter of combining bit-level data to signal-level data. And there will likely be a surprise or two. We can discuss details in a private chat, or steve.hoover@redwoodeda.com.
avinaba123
@avinaba123
okay sir
Steve Hoover
@stevehoover
Congrats to everyone who submitted a FOSSi GSoC proposal. And, good luck! (I was going to share some stats, but I'm not entirely sure that's appropriate, so I'll refrain.)
Syed Farhan
@born-2learn
Thank you Steve. Looking forward to working with FOSSi.
Shivam Potdar
@shivampotdar
Thank you @stevehoover for the wishes! Looking forward to with FOSSi
Shivansh Rakesh
@ShivanshRakesh
Thank you @stevehoover! :)
Vineet Jain
@vineetjain07
Thank you @stevehoover
Ak-Bhatia
@Ak-Bhatia
Thank You @stevehoover
Nazerke Turtayeva
@NazerkeT
Thanks for sharing good wishes @stevehoover , although I am extremely interested with the chosen FOSSI project, I am also not sure whether I ll be selected to continue with. So, could you share please another summer open open-source opportunities in digital design, multicore CPU, GPU, high-speed computing domain?) I really want to grasp my skills in the above-mentioned fields this summer. @jbalkind I would be very happy to hear back your suggestions as well)
awygle
@awygle
Is there an EtherBone python client library?
awygle
@awygle
Also what does the ByteEnable header byte do, exactly? The description in the spec is not clear.
Olof Kindgren
@olofk
@awygle No idea, but my immediate guess would be that it signals if the data is using byte or word granularity. I assume you need to transmit some extra info to indicate which bytes of a words that should be written if you have byte granularity
Stefan Wallentowitz
@wallento
I think at 6pm GMT
Shivam Potdar
@shivampotdar
Hello everyone! I am Shivam Potdar, EE Senior at NITK, India.
Congrats to all the students whose project proposals have been accepted for GSoC.
I am proud to announce that our project proposal "Integration of WARP-V with OpenPiton" has been accepted for GSoC 2020. Special thanks to my mentors Steve Hoover (@stevehoover) and Jonathan Balkind (@Jbalkind) for their continuous help in this process. Thanks to the org admins for considering our proposal and providing me with this opportunity.
I look forward to a great learning experience and connecting with the org members.
Cheers!
Nancy Chauhan
@Nancy-Chauhan
Congratulations to everyone for fantastic summers ahead with GSoC ! All the best
Syed Farhan
@born-2learn
Congrats to everyone who made it into GSoC this year!!
Jonathan Balkind
@Jbalkind
is there a way to run vivado xsim from a different directory than where xvlog/xelab happened?
Olof Kindgren
@olofk
@Jbalkind In a fusesoc/edalize context or in general?
Jonathan Balkind
@Jbalkind
in general
I ended up using a symbolic link to the xsim.dir which seemed to kind of do the job
Steve Hoover
@stevehoover
In case anyone is interested in a fun and highly-visible JavaScript side project, my two GSoC h/w students would be really grateful for some JavaScript expertise. We'd like to put together some visualization of simulations of their CPU designs using new techniques from my startup. (Yes, I am in contact w/ @drom .)
Behdad
@Behdad_sha_twitter
Hello everyone! I have an idea in the field of artificial intelligence that requires hardware design and algorithms to implement. I talked to a few professors at universities and experts in the industry and found some of them interesting, and now I decided to form a team to implement it and use the crowdfunding method to cover its costs. If you would like to participate in this project, I would be very happy to share the details of the idea with you. In the first step, the hardware must be designed and built. I'm very interested in designing it as free hardware. Hope to talk soon. (@Behdad_sha in twitter)
Shashank V M
@ShashankVM
Greetings to all! I would like to create tutorials for LibreCores website. For example, on how to code an FSM in SystemVerilog by following the recommended coding practices. I don't know any web development. But my answers on the electrical engineering stack exchange have been well received, so I believe I would be good at making tutorials. Is there any restriction that the tutorials should use open-source software only? My electrical engineering stack exchange profile https://electronics.stackexchange.com/users/238188/shashank-v-m?tab=profile
What is the procedure to create tutorials? Do I need to know how to design a webpage?
Shashank V M
@ShashankVM
My LinkedIn profile, if it helps https://www.linkedin.com/in/shashankmathew/
Shashank V M
@ShashankVM
I'll open an issue on https://github.com/librecores/librecores-web and see how it works out. I was following this link: https://librecores-web.readthedocs.io/en/latest/contributing.html . That's where I came to know about documentation opportunities at Librecores. I'll probably use WordPress. I had applied for GSOC this year, but did not get selected. So I wish to contribute some technical tutorials for Librecores website on Hardware design using SystemC, SystemVerilog and MyHDL.
Shashank V M
@ShashankVM
If there are any specific guidelines/rules or protocols, please let me know. I also plan to include links to the code on EDA playground so that visitors of Librecores website could simulate the code in their browser for free.
Shashank V M
@ShashankVM
I'd like to point out an issue with Librecores website: https://www.librecores.org/ . When you visit the website, there is a 'learn' heading, under which there is a description "Get started with VHDL, Verilog and other languages. Find out what tools you can use. Learn which licenses are best for your project." The description is misleading as when one clicks on the link "Read the docs": https://www.librecores.org/static/docs , only about publishing/hosting the code and licensing is mentioned. It's not mentioned how to get started with VHDL, Verilog and other languages or which tools can be used. There is nothing to 'learn' as such. Is it because the documentation is incomplete or the description is wrong? I can contribute to the documentation if it's incomplete. I know VHDL, Verilog, SystemVerilog and SystemC.
In the link: https://librecores-web.readthedocs.io/en/latest/contributing.html#creating-documentation-reports-and-tutorials, it reads like this: LibreCores is not just a project repository, but also a community hub for people to get started with digital hardware design. We try to answer questions, such as “What license should I choose?”, “How do I setup a development environment on my PC?”, or “What’s the process to create an FPGA design”? Creating such content, in the form of tutorials, reports, documentations, videos or even interactive forms like games, is a great opportunity to contribute to LibreCores. No coding skills are required, and if you feel that your English is not sufficiently good, don’t worry either! Most of us are not native speakers, and we’ll find someone for proof reading if you wish!
I could not find such content
On Librecores website
Shashank V M
@ShashankVM
So I'm willing to create such content. If someone could guide me on how to get started, I can accomplish this task much faster.
matrixbot
@matrixbot
Christian Svensson Hello :)
Christian Svensson Messages from Gitter looks pretty neat in matrix, sadly Matrix doesn't seem to look as great in Gitter - oh well, I was just happy to find that librecores had a matrix bridge! \o/
Steve Hoover
@stevehoover
Hi @ShashankVM . I was just catching up w/ your discussion. Your objectives w/ SV tutorials may be quite well-aligned w/ a goal of mine. I am preparing to go public w/ a new feature on makerchip.com that enables custom visualization of simulations. This can be very useful for tutorials. Makerchip can serve as the interactive platform for your SV tutorials on Librecores, and users can see the behavior of their circuits.
Shashank V M
@ShashankVM
@stevehoover Sounds good to me. How do I get started?
Steve Hoover
@stevehoover
@ShashankVM I'll provide details in private chat.
eine
@eine
@ShashankVM, ghdl/ghdl#1291 might be useful for you.
Shashank V M
@ShashankVM
Thanks @eine. But it seems that my idea is not a good fit for LibreCores as only open source tools are encouraged. Open source tools do not have most of the features of UVM and SystemVerilog. I don't prefer working with VHDL as it is too verbose.
eine
@eine
@ShashankVM, I'd suggest to give it a try anytime. You might be surprised by open source tooling for VHDL being significantly better than for SV/UVM, and you might be even more surprised about the reduced verbosity by choosing adequate frameworks/methodologies.
Shashank V M
@ShashankVM
@eine, yes I agree that open-source tooling support is better as GHDL supports OSVVM . I will look at ghdl/ghdl#1291 some time. :) Thanks
Taichi Ishitani
@taichi-ishitani

Hi All,
I'm Taichi Ishitani from Japan and I'm developing code generator tool for CSR modules "RgGen". I'd like to introduce RgGen to you.
https://github.com/rggen/rggen

RgGen is a code generator tool to generate source files for CSR modules, such as SystemVerilog RTL, UVM RAL model and Markdown documents, from register map specifications automatically.
Followings are sample register map specifications. You can describe the specification by using Ruby with DSL to describe register map, YAML/JSON and spreadsheet.

Then, RgGen will generate SV RTL, UVM RAL model and Markdown documents. Followings are sample generated source files from the above specification.

I believe RgGen can help your IP development.
Thanks for your attention.

Shashank V M
@ShashankVM
@taichi-ishitani, thanks for sharing.