rggen_default_register
https://github.com/rggen/rggen-sv-rtl/blob/master/rggen_indirect_register.svrggen_indirect_register has also an instance of rggen_register_common. Therefore, I've introduced rggen_default_register to align hierarchy depth of rggen_register_common with an instance of rggen_register_common within rggen_indirect_register.
rggen_register_common has an instance of helper module for simulation. RAL model can execute back door access via this helper module.
hdl_path[0].slices[0].path shows path to an instance of rggen_default_register or rggen_indirect_register.u_register_common.u_backdoor shows path to the helper module.
- https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/reg/sequences/uvm_reg_hw_reset_seq-svh.html
- https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/reg/sequences/uvm_reg_bit_bash_seq-svh.html
- https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/files/reg/sequences/uvm_reg_access_seq-svh.html
Have you tried using SymbiYosys at all?
no I have not yet. What kind of tool?
one of the most complex AXI-lite designs I've examined so far.
This module has a state machine to control request ready and response valid so you think so.
Generated modules may be connected with other modules cascadingly and so, in some case, it will take multiple cycles to get read data.
Therefore, I've implement the bridge module that way.
https://github.com/rggen/rggen-verilog-rtl/blob/700657593c90e34db4f02f2ffc26664bb8939749/rggen_axi4lite_adapter.v#L215
This is handshake logic for write/read response.
- w_bus_valid will be asserted when r_response_valid eq 0
- r_response_valid will be de-asserted when response handshake is completed
Therefore, waveform which you show is strange.
