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Actually, there is interest in hopefully combining VUnit and SVUnit in the future. See https://umarcor.github.io/osvb/intro/index.html:
While VUnit provides multiple optional helper VHDL libraries, the SystemVerilog infrastructure is limited to the HDL runner and some check features. Conversely, SVUnit is for SystemVerilog mostly. The test management features in SVUnit are implemented using Perl, and installation scripts are written in bash/csh. As a result, it would be interesting to handle SVUnit’s HDL resources through VUnit’s simulator interface and runner. There is no work in progress in this regard yet.
Maintainers of VUnit and SVUnit did talk about it, but it's not a priority for any of them.
On the other hand, VUnit was not tested with open source (System) Verilog simulators (iverilog, verilator) for some years now. Nowadays, those might work, which would make it easier for the community to try integrating the SV utilities from SVUnit.
Hello,
I am an assistant professor at Beihang University. Our team is doing a study about GSoC mentors, aiming to understand the motivations, challenges, strategies, and gains of GSoC mentors. To this end, we designed a questionnaire. We sincerely invite GSoC mentors to participate in this survey. Your feedback is very important for us.
Questionnaire link: https://forms.gle/rgAWwmrvrCb5XdAq9
If you are interested in this study, welcome to join our follow-up interview! Thank you very much!
Sincerely,
Xin Tan
Is this project still a requirement or is it a WIP by anyone?
@stffrdhrn Please could you guide me as to how I can start making contributions, being a complete newbie to the Embench platform where would you suggest I start first?
I was thinking maybe I could perform a benchmark on my RPi 4 or BeagleBone Black or ESP32 using some sort of pre-written config files. However upon going through the git repo, I see everything is just very minimal and there is no mention of Xtensa processors which are used in ESP32.
Is this a good way to get started or would you suggest something else?
Also, imo using a platform is way different than writing the source for it, hence are there any issues that I could tackle so that I can also get acquainted with the source code and structure of this project?
Most of the default chip.cfg files are either empty or just have some flags in them. Even the chipsupport.c and h files seem empty in most cases.
I did not follow what you meant by
contribute, create some numbers then put them in a PR
Did you read and run the python script build_all.py
Yes, I briefly did go through and it does pretty much what the documentation says it does, however my doubt is not about that.
What I have done so far and this is the output I am getting:
pi @ embench-iot > ./build_all.py --builddir build --arch arm --chip cortex-m4 --board generic --verbose
Warning: Compilation of beebsc.c from source directory /srv/dev-disk-by-uuid-3c451ce7-c4ad-4424-8933-7a398c9d9e5d/software-dev/embench-iot/support to binary directory /srv/de
v-disk-by-uuid-3c451ce7-c4ad-4424-8933-7a398c9d9e5d/software-dev/embench-iot/build/support failed
Warning: Compilation of main.c from source directory /srv/dev-disk-by-uuid-3c451ce7-c4ad-4424-8933-7a398c9d9e5d/software-dev/embench-iot/support to binary directory /srv/dev-
disk-by-uuid-3c451ce7-c4ad-4424-8933-7a398c9d9e5d/software-dev/embench-iot/build/support failedBasically, it just says that everything fails however does not specify why exactly.
> ./build_all.py --builddir build --arch native --chip speed-test-gcc --board default
aha-mont64
crc32
cubic
edn
huffbench
matmult-int
md5sum
minver
nbody
nettle-aes
nettle-sha256
nsichneu
picojpeg
primecount
Warning: Link of benchmark "qrduino" failed
sglib-combined
slre
st
statemate
tarfind
ud
wikisortnsichneu
picojpeg
primecount
Warning: Link of benchmark "qrduino" failed
sglib-combined
slre
st
statemate
tarfind
ud
wikisort
Hello everyone! Hope you are all doing well. My name is Majd Osseiran, I am a 3rd year Computer Engineering student at American University of Beirut. I have a passion for Computer Architecture/Chip Design. I would like to contribute to the project entitled Create your own LibreCores, or contribute to an existing one.
I am currently working on the design of a Bfloat16 Floating Point Arithmetic Unit. It will be used to add custom RISC-V floating-point instructions to a RISC-V processor that can potentially act as a hardware accelerator for Machine Learning applications.
I am looking for a mentor to help me take this project to the next level. If anyone is interested in mentoring me please let me know and we can discuss ideas. I am also willing to work on a new project that is unrelated to the Bfloat16 unit. I am open to any new ideas. I have so far acquired some experience with FPGA development through coursework and projects. I am comfortable with VHDL and have a solid understanding of logic design and computer architecture concepts, as well as RISC-V ISA.
I am Siddesh Patil, a Second-year undergraduate studying Electronics engineering at Veermata Jijabai Technological Institute, Mumbai.
I have built a 32 bit RISCV CPU Core from scratch using Logisim, focusing on the RV32I ISA.
Also had my hands on the De0 Nano FPGA board to build a Soil Monitoring bot, got proficient with the Verilog language with this project.
Explored Analog Circuit Design with the SYNOPSYS Custom Design Tool Platform.
The project "Giving AnyCore an Open-Source FPU" has fascinated me, and I am interested to work on it.
I am Aditya Tanwar, a second-year undergraduate student in the department of Computer Science and Engineering at the Indian Institute of Technology, Kanpur, India. I have done an introductory course on Mathematical Logic (Course project being implementing a SAT solver) and am currently doing a course about Computer Organization (Course project being tentatively to implement a CPU; we are currently doing assignments in Verilog and MIPS ISA).
I am interested in two project ideas, one of them being "Logical Equivalence Checks with LLHD", which seems to be the intersection of the two courses I find interesting. I wanted to ask where I could start contributing to them.
The other idea I am interested in, is "Giving AnyCore an Open-Source FPU", but I am not exactly sure how to go about "connecting an FPU to a processor" (if it just means implementing floating point algorithms or more), could someone please help me with that? Though I am a beginner in this field, I would be interested in learning and contributing to them too.
Thank you for reading this message!
Hi All,
I just released the latest RgGen v.0.26.0.
https://github.com/rggen/rggen/releases/tag/v0.26.0
Main updates are followings:
- Add new bit field types
- ROWO type
- RW/RO/WO/ROWO with trigger output signals
- Add Wishbone protocol support
- Implement RTL generation only
- Common RTL modules have not been implemented yet
2 replies
Hello everyone,
I am Premraj Jadhav. I am a second-year undergraduate student, pursuing B. Tech in Electronics Engineering at VJTI, Mumbai, India. I am interested in the project 'Minimal RISC-V core with AI Acceleration synthesizable with open source tools'. And I would like to work on it
I have designed and simulated a RISC-V CPU core using RV32I ISA. I have also built a De0 nano FPGA based soil monitoring bot as part of the E-Yantra robotics competition, IIT Bombay. I have knowledge of RISC-V, Verilog HDL as well as FPGA synthesis. I am acquainted with Analog circuit designing on Synopsys custom design tool. Currently I am working with Physically Unclonable Functions (PUFs) on FPGA. I have experience with De0 Nano, Xilinx Zynq ZC702, Altera Cyclone 2, Sipeed Taang Primer fpga boards.
Hi all - the project "Minimal RISC-V core with AI Acceleration synthesizable with open source tools" is proving incredibly popular and my apologies to all who have emailed me and @olofk about this and to whom I have yet to reply. We will assess the all the proposals we receive, and it is probable that at most only one will be approved. Here are some suggestions on what we'll be looking for in the proposal. You should read this in the context of the general GSoC guidelines for students
- what experience you bring to the project and how you will contribute to the FOSSi community
- your vision for what you want to achieve from the project, and how it will benefit you and the community
- a detailed project plan, with milestones and deliverables
- a risk register, to show you understand the uncertainties, and what you might do to mitigate them.
With my background, I'll be paying particular attention to the planning and risks. In the past these have been really important in ensuring that a GSoC project is successful. For the project plan, I suggest breaking down into tasks that can generally be achieved in about one week, and then having a set of milestones that correspond to the tasks that will be achieved in that week. Some of these tasks will be about creating the deliverables from the project.
You should front-load your plan, so you do all the riskiest things first. This gives you the biggest opportunity to fix things when they don't go to plan. And give yourself some time for things to go wrong. One good approach is to aim to have all your core deliverables complete a few weeks before the end. Then has some "stretch" deliverables you can add if everything goes well and you have spare time.
Things will not go to plan - if they do, then the project is too easy. GSoC projects should stretch the participant. This is where the risk register comes in. Thinking ahead about what could go wrong, and how you minimize the impact of things going wrong. One approach you can use is as follows
- think about all the (significant) things that could go wrong
- assign a score to the impact (I) of that risk from 1 (minimal effect on the project) to 3 (kills the project)
- assign a likelihood (L) of the risk happening from 0 (won't happen) to 10 (certain to happen) . In practice 0 and 10 are not meaningful, since they are not risks, but certainties one way or another
- compute I x L and provide a mitigation (i.e. steps to reduce the risk) for any risk where I = 3 or I x L > 10.
Typically you might have 5-10 risks you have assessed. Mitigations can be things like
- starting a particular task early, to determine if the risk will materialize and then having an alternative approach
- providing multiple solutions to a problem, to increase the chance that one will work
The risk register will become a living document throughout the project, allowing you to plan ahead as risks change.
I hope these suggestions prove useful. They are only suggestions - it is for you as the student to present your proposal in the way that is best for you.
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