@stevehoover Sir in this project detail it is defined as we have to build scripts to map RTL signal names to their original TL-Verilog names. So there will be some .csv file which will map. Am I right?
@avinaba123 TL-Verilog tools are capable of generating SystemVerilog that defines signals using TL-Verilog naming conventions and hierarchy that are assigned to their Verilog/SystemVerilog counterparts. This can be used, or tools can be modified to produce CSV or similar mappings. I don't think there's much complexity to this project; it's mostly parsing of the output of various synthesis tools. But there is the matter of combining bit-level data to signal-level data. And there will likely be a surprise or two. We can discuss details in a private chat, or steve.hoover@redwoodeda.com.
Thanks for sharing good wishes @stevehoover , although I am extremely interested with the chosen FOSSI project, I am also not sure whether I ll be selected to continue with. So, could you share please another summer open open-source opportunities in digital design, multicore CPU, GPU, high-speed computing domain?) I really want to grasp my skills in the above-mentioned fields this summer. @jbalkind I would be very happy to hear back your suggestions as well)
Hello everyone! I am Shivam Potdar, EE Senior at NITK, India.
Congrats to all the students whose project proposals have been accepted for GSoC.
I am proud to announce that our project proposal "Integration of WARP-V with OpenPiton" has been accepted for GSoC 2020. Special thanks to my mentors Steve Hoover (@stevehoover) and Jonathan Balkind (@Jbalkind) for their continuous help in this process. Thanks to the org admins for considering our proposal and providing me with this opportunity.
I look forward to a great learning experience and connecting with the org members.
Cheers!
Congrats to all the students whose project proposals have been accepted for GSoC.
I am proud to announce that our project proposal "Integration of WARP-V with OpenPiton" has been accepted for GSoC 2020. Special thanks to my mentors Steve Hoover (@stevehoover) and Jonathan Balkind (@Jbalkind) for their continuous help in this process. Thanks to the org admins for considering our proposal and providing me with this opportunity.
I look forward to a great learning experience and connecting with the org members.
Cheers!
I ended up using a symbolic link to the xsim.dir which seemed to kind of do the job
In case anyone is interested in a fun and highly-visible JavaScript side project, my two GSoC h/w students would be really grateful for some JavaScript expertise. We'd like to put together some visualization of simulations of their CPU designs using new techniques from my startup. (Yes, I am in contact w/ @drom .)
Hello everyone! I have an idea in the field of artificial intelligence that requires hardware design and algorithms to implement. I talked to a few professors at universities and experts in the industry and found some of them interesting, and now I decided to form a team to implement it and use the crowdfunding method to cover its costs. If you would like to participate in this project, I would be very happy to share the details of the idea with you. In the first step, the hardware must be designed and built. I'm very interested in designing it as free hardware. Hope to talk soon. (@Behdad_sha in twitter)
Greetings to all! I would like to create tutorials for LibreCores website. For example, on how to code an FSM in SystemVerilog by following the recommended coding practices. I don't know any web development. But my answers on the electrical engineering stack exchange have been well received, so I believe I would be good at making tutorials. Is there any restriction that the tutorials should use open-source software only? My electrical engineering stack exchange profile https://electronics.stackexchange.com/users/238188/shashank-v-m?tab=profile
What is the procedure to create tutorials? Do I need to know how to design a webpage?
I'll open an issue on https://github.com/librecores/librecores-web and see how it works out. I was following this link: https://librecores-web.readthedocs.io/en/latest/contributing.html . That's where I came to know about documentation opportunities at Librecores. I'll probably use WordPress. I had applied for GSOC this year, but did not get selected. So I wish to contribute some technical tutorials for Librecores website on Hardware design using SystemC, SystemVerilog and MyHDL.
I'd like to point out an issue with Librecores website: https://www.librecores.org/ . When you visit the website, there is a 'learn' heading, under which there is a description "Get started with VHDL, Verilog and other languages. Find out what tools you can use. Learn which licenses are best for your project." The description is misleading as when one clicks on the link "Read the docs": https://www.librecores.org/static/docs , only about publishing/hosting the code and licensing is mentioned. It's not mentioned how to get started with VHDL, Verilog and other languages or which tools can be used. There is nothing to 'learn' as such. Is it because the documentation is incomplete or the description is wrong? I can contribute to the documentation if it's incomplete. I know VHDL, Verilog, SystemVerilog and SystemC.
In the link: https://librecores-web.readthedocs.io/en/latest/contributing.html#creating-documentation-reports-and-tutorials, it reads like this: LibreCores is not just a project repository, but also a community hub for people to get started with digital hardware design. We try to answer questions, such as “What license should I choose?”, “How do I setup a development environment on my PC?”, or “What’s the process to create an FPGA design”? Creating such content, in the form of tutorials, reports, documentations, videos or even interactive forms like games, is a great opportunity to contribute to LibreCores. No coding skills are required, and if you feel that your English is not sufficiently good, don’t worry either! Most of us are not native speakers, and we’ll find someone for proof reading if you wish!
I could not find such content
On Librecores website
Christian Svensson Messages from Gitter looks pretty neat in matrix, sadly Matrix doesn't seem to look as great in Gitter - oh well, I was just happy to find that librecores had a matrix bridge! \o/
Hi @ShashankVM . I was just catching up w/ your discussion. Your objectives w/ SV tutorials may be quite well-aligned w/ a goal of mine. I am preparing to go public w/ a new feature on makerchip.com that enables custom visualization of simulations. This can be very useful for tutorials. Makerchip can serve as the interactive platform for your SV tutorials on Librecores, and users can see the behavior of their circuits.
@eine, yes I agree that open-source tooling support is better as GHDL supports OSVVM . I will look at ghdl/ghdl#1291 some time. :) Thanks
Hi All,
I'm Taichi Ishitani from Japan and I'm developing code generator tool for CSR modules "RgGen". I'd like to introduce RgGen to you.
https://github.com/rggen/rggen
RgGen is a code generator tool to generate source files for CSR modules, such as SystemVerilog RTL, UVM RAL model and Markdown documents, from register map specifications automatically.
Followings are sample register map specifications. You can describe the specification by using Ruby with DSL to describe register map, YAML/JSON and spreadsheet.
- https://github.com/rggen/rggen-sample/blob/master/block_0.rb
- https://github.com/rggen/rggen-sample/blob/master/block_0.yml
- https://github.com/rggen/rggen-sample/blob/master/block_0.xlsx
Then, RgGen will generate SV RTL, UVM RAL model and Markdown documents. Followings are sample generated source files from the above specification.
- https://github.com/rggen/rggen-sample/blob/master/block_0.sv
- https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv
- https://github.com/rggen/rggen-sample/blob/master/block_0.md
I believe RgGen can help your IP development.
Thanks for your attention.