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Oleg Nenashev
@oleg-nenashev
@stevehoover if you could share contacts of Akos, it would be much appreciated. I plan to recover the LibreCires/FOSSi developer huddles, and I would really like to invite Akos to preswnt there. I liked the talk a lot
ahadnagy
@ahadnagy
@oleg-nenashev I'm here in the chatroom, DM me :)
Oleg Nenashev
@oleg-nenashev
:+1:
Christian Svensson
@bluecmd
I've been wondering about best practices for power management for FPGA designs. I have a design that has 4x SFP ports and it seems to me that it would be a good idea to shut down the TX/RX pipelines if there is a loss of signal - or no SFP at all - on that port. I don't really know what's the best way to implement that
Holding reset for the pipeline? Disabling the clock (which would add a metric ton of clock domain crossings I guess?)? Adding an "enable" port of all parts and tie them together?
I've found surprisingly little information about this in the Altera / Intel Stratix documentation
myarena-mk07
@myarena-mk07
From where i should pick up the project?
Is it from Fossi github community or from my choice?
Nancy Chauhan
@Nancy-Chauhan
Hello @myarena-mk07 , you can have gsoc 2019 ideas at https://fossi-foundation.org/gsoc19-ideas
umarcor
@umarcor

Hi @ahadnagy! Nice to find you here! We talked at ORConf and I asked you about the (javascript) tools you used to build the knobs and sliders in the web frontend of your remote framework. I saw that you contributed mostly to https://github.com/alessandrocomodi/fpga-webserver this past summer. I assume, as part of the 'Hardware Accelerated Web Applications' GSoC mentored by @@stevehoover.

As commented, I found your talk really interesting because I've been working on a GUI (web) frontend to provide custom real-time visualizations for HDL simulation of complex design/algorithms. Should I have been aware of ORConf earlier, I should have submitted a lightning talk to foster the discussion... Anyway, you can find three screencasts in https://github.com/VUnit/vunit/pull/476#issuecomment-496632427. The TL;DR is that any memory buffer (array of values, BRAM, FIFO, etc.) inside the HDL design (no matter how deep in the hierarchy) can be mapped to any Web visualization model. In the examples, a large table, two small tables and rendered images are shown, respectively. Those examples are based on VUnit + GHDL + Flask + Vue.js; nonetheless, I have successfully reproduced the setup using Octave (C++), instead of Python. The same binaries can also be used with DBM tools (e.g. MAMBO or DynamiRIO) (see dbhi).

The targets of fpga-webserver and my approach are slightly different, but I believe there are lots of overlapped implementation details. The first PR of the contributions to VUnit that provide built-in Python/C and VHDL co-execution is about to be upstreamed (VUnit/vunit#507). Therefore, I'd like to discuss possible areas of collaboration, before planing the next PRs. For example, IIRC, in http://fractalvalley.net/ the C++ models are built with Verilator, isn't it?

I don't know if this is the best room to talk about CLaaS, or if some other channel might better fit the discussion. I can also open an issue in alessandrocomodi/fpga-webserver, should you prefer.

Steve Hoover
@stevehoover
@umarcor , looks interesting. We have a "fpga-webserver" room that is a good place to chat.
umarcor
@umarcor
@stevehoover, may I know the specific name/link to that room? I didn't find it in the README.
Steve Hoover
@stevehoover
Christian Svensson
@bluecmd
https://www.librecores.org/bluecmd/fejkon heh, apparently my FPGA project is written in "Tcl/Tk"
I mean, it's not wrong - there is a lot of it - but maybe not what's the intention ;-)
findnabeel
@findnabeel
Hi All, I just uploaded a project in LibreCores by linking the github page. But looks like any further change in the github readme is not getting reflected in the librecore site.
Anyone faced similar problem? Any solution ?
Jonathan Balkind
@Jbalkind
it might only update with some frequency? I feel like I've seen something similar before
Amitosh Swain Mahapatra
@agathver
@findnabeel Can you give me a link to your project for further debugging what's going on? I believe we fixed this issue back in April. Updates should automatically be picked up
findnabeel
@findnabeel
Jonathan Balkind
@Jbalkind
The FOSSi foundation twitter links to a manifesto but said webpage doesn't seem to exist
Am I the only one suffering this?
umarcor
@umarcor
@Jbalkind, I can confirm.
Dan Gisselquist
@ZipCPU
@olofk (or whoever): At the last ORCCONF, a week and a half ago now, @wallento suggested that the WB spec was being updated. I'm currently maintaining a set of formal properties that I use to know if something meets spec or not. Can anyone tell me where the conversations are taking place regarding this update?
Amitosh Swain Mahapatra
@agathver
@findnabeel Ok, for now I manually triggered an update. Looks like we haven't set up github webhooks for this repository. It is either due to missing permissions or due to some other reason. @imphil can you check what happened?
Stafford Horne
@stffrdhrn
@ZipCPU hi, @imphil mentioned there is a mailing list where they are discussing the new version. You will have to get him to add you too the list.
I mean @wallento is maintaining the list.
Philipp Wagner
@imphil
@ZipCPU Please have a look at https://github.com/fossi-foundation/wishbone. You can file issues there, and there's also a link to the mailing list. I haven't seen much discussion on the list yet about wishbone yet through, but feel free to start a new thread if something should be addressed.
@Jbalkind website is fixed now
@findnabeel please file a bug at https://github.com/librecores/librecores-web/issues if updates don't work for any reason. And as workaround in the meantime, can manually update by appending a /update to the end of your project URL.
Stefan Wallentowitz
@wallento
Sorry, I am delayed, but we plan to open a call for improvements towards wishbone B3.1
The repository is the one that Philipp pointed out
Dan Gisselquist
@ZipCPU
Cool! I've signed up for the mailing list
findnabeel
@findnabeel
@agathver Thanks.
@imphil Thanks . Sure will file the bug.
Aquib Baig
@aquibbaig
Hi, @imphil @agathver Is librecores down currently for some reason?
Waffle552
@Waffle552
When was this project started?
Steve Hoover
@stevehoover
@oleg-nenashev I was just watching your ORConf update on LibreCores CI. I see several synergies between LibreCores CI and 1st CLaaS going forward. Most obvious would be using 1st CLaaS for CI of FPGA runs on F1. You mention using cloud FPGAs and Kubernetes to bring up FPGA as a microservice, and that's exactly what 1st CLaaS is. (BTW, I think you are underestimating the effort to make this work.) If not sooner, we should talk before the next GSoC proposals (assuming it happens again). Did you and @ahadnagy talk at ORConf?
Oleg Nenashev
@oleg-nenashev
@stevehoover Hi. Yes, I had a plan to talk to @ahadnagy after ORConf and to invite him to the LibreCores Contributor huddles. But than life happened and I had no time to really do so :( Still in my list
Steve Hoover
@stevehoover
Ok, @oleg-nenashev . Reach out anytime.
ZerononcenseMarkets
@ProofofTrade_twitter
Hello
Anyone here in the chat?
Would love to speak with you all about something that's extremely imporatant. I run a 'libre' organization as well.
@stevehoover Let's speak.
Nancy Chauhan
@Nancy-Chauhan
@oleg-nenashev @stevehoover @eahmedsalman will like to work along on this . Do include me too in huddles to have more idea regarding this
Steve Hoover
@stevehoover
Call for Papers: 2nd Workshop on Open-Source Design Automation -- OSDA 2020 https://www.linkedin.com/pulse/call-papers-2nd-workshop-open-source-design-osda-2020-steve-hoover
Arzoo
@arzoo14
Hello everyone!
I am Arzoo, a fifth-year student at the National Institute of Technology, Hamirpur pursuing Computer Science & Engineering (Dual-Degree). I am looking for GSoC 2020. Please guide me on how do I start contributing to the organization.
Thanks and Regards,
Arzoo
Nancy Chauhan
@Nancy-Chauhan
Hey, @arzoo14 Welcome ! you can have look at https://fossi-foundation.org/gsoc19-ideas to start contributing with. Also for librecores web, which serves as the common platform, to share projects and ideas, in the area of open-source digital hardware design. you can start exploring https://github.com/librecores/librecores-web/issues?q=is%3Aissue+is%3Aopen+sort%3Aupdated-desc issues for librecores web.
ridhishjain
@ridhishjain
Hello everyone, myself Ridhish Jain, IIT Dhanbad. I am a web developer and want to actively contribute in this organization for GSoC'20. From where do I start, or can u suggest me some project?
Steve Hoover
@stevehoover
@ridhishjain , see @Nancy-Chauhan 's response, above. 2020 ideas have not yet been collected.