librecores/Lobby

LibreCores Discussion

Dan Gisselquist

@ZipCPU

I'm not sure if/where it's being "maintained" though

Altus Tek

@altustek

@ZipCPU do you know the usart16550 is released under what open source license ?

Dan Gisselquist

@ZipCPU

It should say within the repo

Altus Tek

@altustek

no its not, so I am asking :-)

Dan Gisselquist

@ZipCPU

Hmm ...

Altus Tek

@altustek

I think its GNU LGPL, thats what is typed into the verilog files

Dan Gisselquist

@ZipCPU

If that's in the Verilog, then that's what it is.

Jonathan Balkind

@Jbalkind

I've heard some people say that that uart may not be entirely 16550 compliant

I think someone working on microwatt maybe?

Altus Tek

@altustek

Dan Gisselquist

@ZipCPU

I wouldn't know

Jonathan Balkind

@Jbalkind

I don't think it was necessarily a big thing

some minor detail about the interrupt wire not being deasserted in some condition

don't really remember

Tim Ansell

@mithro

OpenRAM on SKY130 talk from Matt as part of FOSSi Foundation DialUp talk series is starting in 10 minutes -- https://youtu.be/9Lw83kFtnc4

Altus Tek

@altustek

Great Talk @mithro

Muhammad Salman Afzal

@muhammadsalmanafzal

Hey there, hope you are all doing well. I'm thinking of doing my final year project on RISCV. The area can be RISCV verification or ISP, Debug for the in-house generated bare-metal core. I have a made a core in Verilog supporting RV32IM and currently working on the F extension. So, I know a thing or two on the design part. Can anyone tell me which would be a better project complexity wise since I'm doing it all alone (due to certain conditions at our university), so, I don't want to take on something that is too hard to solve. Can anyone briefly tell me how to proceed in each case since both things will be new to me? Thanks.

Dan Gisselquist

@ZipCPU

muhammadsalmanafzal: Does that mean you'll need to build a RISCV core?

Sigh. He left.

Muhammad Salman Afzal

@muhammadsalmanafzal

not necessarily

I can test whatever I make on an already developed core as a test case

Dan Gisselquist

@ZipCPU

<muhammadsalmanafza: Do you know of a RISC-V core you'd like to test? And, also, are you familiar with riscv-formal?

Dan Gisselquist

@ZipCPU

For some CPU's, the work would be more involved than others

Muhammad Salman Afzal

@muhammadsalmanafzal

For some CPU's, the work would be more involved than others

We'd like to develop something parametrized that anyone can configure according to their needs. Like if someone wants to remove the verification of M extension, they can do so with a little effort. Is something like this can be done? Can you give me starting point about what I may need like some resources to get me up and running?

Dan Gisselquist

@ZipCPU

muhammadsalmanafzal: So far, what you've described has been done in riscv-formal

Steve Hoover

@stevehoover

In case anyone thought coding a CPU would be too hard: https://riscv.org/blog/2020/11/13-year-old-nicholas-sharkey-creates-a-risc-v-core/

Shivam Awasthi

@the-good-boy

Hello!

Deepak S

@Deepak-suresh14

Hello, can anybody guide me through the first steps that I need to take for open source contributions.

GlenNicholls

@GlenNicholls

@Deepak-suresh14 There is not a guide about such an open-ended request, even for software. There are "best practices" depending on the application/language/CM tool/company/etc, but it is project dependent. Do you have a specific project in mind that you would like to start? Are there any open source tools that you would like to contribute to?

Shivam Awasthi

@the-good-boy

Hello! My name is Shivam Awasthi. I am a second year Engineering graduate in India. I want to start contributing in some projects, so that I can get familiar with the code. I want to participate in GSoC next year. I would like to explore the code of fractalvalley.net and hopefully, I can contribute for its frontend. Can someone please tell how I can get started? Thanks!

Jonathan Balkind

@Jbalkind

@the-good-boy you may want to check out the warp-v channel

Deepak S

@Deepak-suresh14

@GlenNicholls thanks I will take a look at what can I do.

Deepak S

@Deepak-suresh14

Hello, Everyone I finally completed the tutorials on TL-Verilog at Makerchip.com , really enjoyed it , now moving on to next steps . Suggestions are Welcomed.

Steve Hoover

@stevehoover

Hi @Deepak-suresh14 I've given you an invite to the TL-V Users Slack group. You can brainstorm w/ folks there and/or find inspiration from https://fossi-foundation.org/gsoc20-ideas and https://github.com/stevehoover/TL-V_Projects .

Deepak S

@Deepak-suresh14

@stevehoover Sure sir, Thank you

Rohan Juneja

@rohanjuneja

Hello! My name is Rohan Juneja. I am a first year PhD student, and my background is from CPU RTL Designing. I am looking forward to apply for GSOC 2021.
Could someone please help me with how can I get started getting familiar with the projects going on at Fossi foundtion?
Thanks!

Steve Hoover

@stevehoover

@rohanjuneja Last year's GSoC ideas list is a good start: https://fossi-foundation.org/gsoc20-ideas

Shivam Awasthi

@the-good-boy

@stevehoover I have gone through the TL-Verilog basics and the tutorials on Makerchip IDE. Can you give me access to TL-Verilog Slack group so that I can get more help and interaction there? Thanks.

1 reply

Digvijay Singh

@JayDigvijay

@stevehoover I have completed the TL-Verilog tutorial on Makerchip IDE. Please add me to the TLV Slack group as I am eager to start contributing and wish to apply for GSoC '21. Thank You!

5 replies

Deepak S

@Deepak-suresh14

@JayDigvijay you can see the idealist at https://www.fossi-foundation.org/gsoc20-ideas and let everyone know what interest's you. Thank You!

Digvijay Singh

@JayDigvijay

@Deepak-suresh14 I went through, I would like to start with 'Integration of Warp-V with RISC-V'. Where do you recommend I should start?

Digvijay Singh

@JayDigvijay

@stevehoover I have joined the warp-v channel on gitter, and have perused the GitHub repo. Since there is currently no support for cache and IOs, I was thinking if it might be possible for me to contribute to that... What do you recommend?

1 reply

Kaleb Barrett

@ktbarrett

is a project owned by the FOSSi Foundation and deserves some representation on their GSoC project list. Who do I contact about adding to the GSoc list?

Olof Kindgren

@olofk

@ktbarrett Yes! Definitely. Would be great to have some cocotb projects. The first thing we need to find is potential mentors for such projects. Would you be able to mentor or know anyone who can?

Kaleb Barrett

@ktbarrett

@olofk Yes I would be able to mentor.

Olof Kindgren

@olofk

@ktbarrett Perfect. I will be helping out on the organization side together with @Jbalkind @wallento and @imphil . I just copied our old ideas page here as a starting point. Feel free to submit a PR with ideas or get in touch with us if you want to discuss it a bit first

eine

@eine

@olofk, https://github.com/fossi-foundation/fossi-foundation.github.io/blob/master/gsoc21-ideas.md#vhdl-front-end--for-yosys is outdated. Please, see https://github.com/ghdl/ghdl/wiki/Ideas:-GSOC.

Olof Kindgren

@olofk

@eine Thanks. I'll get it removed. There are likely more outdated ones so would be great if everyone with proposals from last year took a look

2 replies

ljx-jiangnan

@ljx-jiangnan

I joined tonight and I am very new to everything. I am studying multi-interface protocol conversion and want to make a new ip core. Is it possible that I can contribute something

Jonathan Balkind

@Jbalkind

@stevehoover that's what Olof sent the link to above (https://github.com/fossi-foundation/fossi-foundation.github.io/blob/master/gsoc21-ideas.md) so feel free to PR that

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