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Pranav Lulu
@lulu9312
2) Giving Anymore an Open Source FPU. Are there any prerequisites which I should look upon @Jbalkind @olofk . Thanks.
Dexdd
@Dexdd
Hey guys, I am Deeksha, a senior at International Institute of Information Technology, Hyderabad, India. I have gone through the prerequisites required for SERV and RISC architecture. @olofk give me a way to proceed to contribute to the github on the below written project. I am working on project Compressed instruction support for SERV.
Mohammad Shahanhsa
@mdshahansha

Hi!

I'm Shahansha, a student at Heritage Institute of technology. I have experince from last more than 1 year in my journey as a developer and have worked with HTML, CSS, JS,java, Bootstrap 4, Python3, C/C++,mongoDB, MySQL to enchance MY creativity.

Im interested to enchance develops, enhances, tests and web content applications with an end goal of creating engaging and user-friendly site layout and function, I'm much fascinated to be a part of the community, learn and contribute In Gsoc.

Thank You!!

Shashank V M
@ShashankVM
Hi everyone. I'm Shashank, a final year student of ECE at St Joseph Engineering College. I had applied last year but did not get selected. I aspire to be an open-source hardware developer like Stafford Horne. I also wish to get employed as a software developer in the near future. I will apply for GSOC again this year, and I wish good luck to the other GSOC aspirants!
Zeeshan Rafique
@zeeshanrafique23
Hello everyone,
I am Zeeshan Rafique from Karachi Pakistan. I saw all of the projects of the FOSSI foundation, I found two projects that are meeting my expertise, and those are
1) Compressed instruction support for SERV: mentored by @olofk
I review the code of SERV core that looks quite satisfying and readable, adding C-extension can reduce the size instruction memory with the tradeoff: addition of few gates in the core. I had implemented Compressed instruction with my RV32IMC core a few months ago and I am also working on Ibex(low-RISC) and also tape-out one SoC and send in Google shuttle for fabrication- thanks to FOSSI.
2) Giving AnyCore an Open-Source FPU
I am currently adding the FPU with Ibex for the next tapeout (I used the PULP opensource FPU named 'fpnew') and I am almost done with that (https://github.com/zeeshanrafique23/azadi), so designing a new and opensource FPU wouldn't be a big deal.
Please let me know who is mentoring the 'Giving AnyCore an Open-Source FPU' project.
Thanks,
Zeeshan Rafique
lakshmi-sathi
@lakshmi-sathi

Hi,

I had sent a mail expressing my interest to contribute to the organization this summer and an idea which I am interested to work upon. It was the day before yesterday (to the foundation's GSoC ID). I haven't received a response yet and was wondering if you would advise that I wait some more or that I try reaching out here?

Thanks,
Lakshmi S

Olof Kindgren
@olofk
Hi everyone,
It's great to see so much interest in GSoC this year. We haven't had time to respond to all of you yet, but please stay around and get familiar with the community. I would also like to mention that our good friends at SymbiFlow https://symbiflow.github.io/ are participating in GSoC as well
Zeeshan Rafique
@zeeshanrafique23
Great to hear.
Ninad Jangle
@ninja3011

Hello Everyone!

I am Ninad Jangle, from India. I am a sophomore pursuing a degree in Electronics Engineering. I took my time exploring across multiple domains of GSOC. I gained an interest in RISC V and Verilog about a month ago. Though I am fairly new at it, I get very excited as I learn more about them.

I recently completed the TL-Verilog edx course by Steeve Hoover, and will start looking into blocky implementation now.

I found two projects that I am looking forward to contribute to and somewhat meet my skill level.

1) Block-Based Circuit Design:

I remember when I first got an Arduino, I was too much of a novice to understand anything. I had used a blocky type software for writing a simple, program to blink lights using a mobile app. These types of software can be incredibly powerful for getting new users initiated into systems. Learning Verilog and TL-Verilog have been vastly different experiences, TL Verilog has an incredible educational value. By contributing to this project I hope to make that value more accessible to the lower level of skill sets and age groups.

2) Giving AnyCore an Open-Source FPU

I started looking into AnyCore. I haven't done anything of this sort of project earlier, but I have done a fair reading of the tools required. I am reading The AnyCore documentation, FPU theory, doing Verilog examples from online lectures and familiarizing myself with RISCV theory. Being selected for this project will be a tremendous learning opportunity for me.

If the mentors or any of the fellow applicants can guide me on how best to prepare for this projects, please hmu!

I have decided only to apply to these two Fossi projects in GSOC.

Shashank V M
@ShashankVM
@olofk I noticed you have put up the project "Compressed instruction set for SERV CPU" on both RISC-V Mentorship 2021 and FOSSi GSOC 2021. It's unclear how 1 project can be sponsored from 2 sources. https://mentorship.lfx.linuxfoundation.org/project/77a20898-9a3f-4f6c-aa8d-62883883f711
Olof Kindgren
@olofk
@ShashankVM That's a legitimate concern. I talked to the LFX people about this idea a long time ago before we knew if FOSSi Foundation would be accepted into GSoC and said I might not be able to do it if we were. It's unfortunate that the application period for LFX and GSoC opened at the same time. I will do something about this
Steve Hoover
@stevehoover
@ninja3011 I'm excited about that one (blockly), too. Do you have experience with javascript? This is a project where, now that you've done some TLV, the best way to learn about it is to dive into blockly and try stuff.
Ninad Jangle
@ninja3011

@stevehoover , Yeah! I have been looking into blocky. Playing with it a bit. There isnt much documentation on creating custom language generators though.

I still found 2 good sources:

https://blocklycodelabs.dev/codelabs/custom-generator/index.html?index=..%2F..index#8
https://groups.google.com/g/blockly/c/MBv7GtZ-uVc/m/t2aeD9xbAAAJ?pli=1

I am referring these to plan a custom TL Verilog generator.

I have worked with JavaScript extensively in a course in the past. It's been a while though so I am revising it again now.

1 reply
Zeeshan Rafique
@zeeshanrafique23
Is there any standard proposal template for FOSSI foundation projects? or I can use generic?
sidastro30
@sidastro30

Hello, everyone can anyone suggest to me some project to involve
I am Siddharth like to learn more about hardware development around RISC-V ecosystem by contributing to it
currently following this course:"Building a RISC-V CPU Core by edx" to get to know more about TL-Verilog & RISC-V ecosystem
In past successfully complete these course to get exposure of FPGA hardware development
1.Effective Verilog Learning with Intel and Xilinx FPGAs by UDEMY
2.VSD-Physical Design Flow by UDEMY

Academically having understanding of these subjects:
VLSI> digital & analog VLSI || Architectural design of ICs || VLSI Cad
Embedded> Embedded Software Design and Validation ||Security Aware CPS & IOT Design||Embedded Communication Networks

Past experience involved in developing embedded based project/products on atmel,stm based architecture

1 reply
Olof Kindgren
@olofk
@zeeshanrafique23 No templates available.
Zeeshan Rafique
@zeeshanrafique23
Ok, thanks.
MJVARMA
@MJVARMA
Hello everyone my name is MJ Varma, from India. I am currently pursuing my degree in Electronics and communication. I have basic knowledge on verilog and FPGA design and want to amplify that using this oppurtunity. I just started the course "Building a RISC-v CPU Core" to get my pre requistes on the project I want to work on. I have completed a course on IC physical Design which got more interested in this topic.
Can someone help me how do I get started?
MJVARMA
@MJVARMA
I want to contribute to this project "WARP-V TensorCore Extension for Deep Learning" because it meets only some part of my skill set and I can learn more things on my way
Theodore Omtzigt
@Ravenwater
@MJVARMA Great to hear you are interested in the TensorCore project. There are a handful of different angles we can take depending on your interest and skill level.
Kartikey rai
@kartikeyrai-me
Hello everyone, my name is Kartikey, and I am from India. I am currently a Pre - Final year student at Bennett University, and is pursuing my degree in Electronics and Communication Engineering. In past, I have worked on designing RISC - V where I implemented entire RV32I instruction set along branch prediction core using Verilog as HDL and Xilinx Vivado. At the time when I am writing this message, I currently have around 1.5 years of coding in Verilog, and along with RISC - V core, I have worked on other projects using Verilog.
I wanted to contribute to this project "RISC-V core with AI Acceleration synthesizable with open source tools" because it meets part of my skill set and I can learn more things on my way.
Dan Gisselquist
@ZipCPU
Welcome, Kaptain-99!
Kruti Deepan Panda
@krutideepanpanda
Hello everyone, I am Kruti. I am a 2nd year ECE student. I have basic knowledge of Verilog and have made a simple microprocessor. I am very much interested in learning more about RISC-V, especially on the project Idea "Compressed instruction support for SERV". I would like to contribute to it whether or not I get GSoC.
Anjani K shukla
@skanjani
nice spirit @krutideepanpanda! I hope that you will get selected.
Hello Everyone, I am Anjani, a pre-final year student at SATI India. I am preparing for the "Logical Equivalence Checks with LLHD" project as a GSoC student. I hope I will make some good friends here from FOSSi and librecores community.
I successfully build the CIRCT project and start searching for good first issue to take on before the application deadline.
Nitish-byte
@Nitish-byte
Hello everyone, I'm Nitish, a final year Electronics and telecommunication student at SPIT. I was interested in block-based circuit diagram. How should I start working on my proposal, any ideas?
Anjani K shukla
@skanjani
Hi @Nitish-byte! Looking at description of project it seems you must familiar with TL-Verilog, If you are not please visit their website and complete a tutorial. You should also familiar with MIT Scratch project. You should try to build the project and fix one or two issue. It may give some confidence to you. Also gives a better impression in you project proposal. All the scratch projects are under LLK organization on GitHub. See the link- https://github.com/LLK. Then you should also make yourself familiar with Google Blocky project. I see there is also a blocky-sample project under the same google organization. You might want to try a few example. Again fixing some minor issues from Blocky project will surely give a bright impression on your prospective mentors. Good luck for application!
Usman Zain
@usmnzen_twitter

Hello, I'm Usman, a final year computer science undergrad. I have designed a risc v 5 stage pipelined core, implementing the rv32i instruction set to get an idea of the opensource hardware. Currently, i am working on a software development kit that will program our SoC that @zeeshanrafique23 is leading.

I would like to like work on projects in the software domain that we can take as part of gsoc2021, if anyone is interested or has any ideas, please discuss. Thanks

Zeeshan Rafique
@zeeshanrafique23
Nice to see you here. @usmnzen_twitter
Steve Hoover
@stevehoover
Sorry for the delayed response, @Nitish-byte . I thought Dr. Mheta would reply, but she doesn't seem to be on Gitter. I've pinged her. Thanks, @skanjani for an on-point response to Nitish.
Anjani K shukla
@skanjani
NP @stevehoover, I am always happy to help new comers.
Nitish-byte
@Nitish-byte
Thank you @skanjani for the response, I'll start working on points that you've suggested. It's fine @stevehoover I just wanted the general idea on how to start working.
2019moaazkhaled
@2019moaazkhaled

Hi, I am moaaz, a senior student in nano-electronics department,
I have a good experience in Verilog and VHDL for both FPGA and ASIC flows. with a one year freelancing in the field of digital VLSI.

I want to participate in one of the projects propossed by FOSSI foundation in GSOC this year,
But I don't know how to communicate with the mentor !!!!

can anyone help me ?

2 replies
Shahzaib Kashif
@shahzaibk23

Hi, I am Shahzaib, a 3rd year Software Engineering Student. I have 2 years experience of working with HDLs and RISC-V ISA.

I am interested in working on Block Based Circuit Designing Project. Is anyone else also writing a proposal for that?

1 reply
2019moaazkhaled
@2019moaazkhaled
I wounder if it is available to participate in a project with a team of my colleges or not ?
1 reply
Shahzaib Kashif
@shahzaibk23

Hi, I am interested in working on Block Based Circuit Design Project.

I have submitted the draft proposal for that.
@gmehta_gitlab @stevehoover

Kindly review my proposal, all kinds of recommendations and suggestions are appreciated.

1 reply
2019moaazkhaled
@2019moaazkhaled
now I will start writing my proposals for two projects, I have just three days,
could any one help me with some tips?
Adithya Sunil
@adithyasunil26
Hello, I am Adithya Sunil and I am a 2nd-year Electronics and Communication Engineering student at IIIT Hyderabad. I have previously worked with verilog for various projects and assignments and I have some experience working with ISAs. I found the project idea for porting the BaseJump STL to FuseSoC quite interesting and I have submitted a draft proposal for the project. It would be very helpful to me if my proposal can be reviewed by a mentor so I can use the feedback to fix the shortcomings.
Thank you!
Nitish-byte
@Nitish-byte
Hello @stevehoover & @gmehta_gitlab , I have shared my draft proposal for block based circuit design, could you please review it and share the feedback.
Kartikey rai
@kartikeyrai-me
Respected @stevehoover and @Jbalkind, I have shared my draft proposal for Integration of WARP-V with OpenPiton via mail. Can you please review it and share the feedback.
Thank you!
Steve Hoover
@stevehoover
Will do, guys.
Elisa Silva
@minifyit_twitter
Hello everyone!
Elisa Silva
@minifyit_twitter
I'm brazilian C.S. student looking for a final project that involving Verilog and RISC-V. I'm got very interested in the project proposed by @olofk but looks like other people that have more experience in the topic are applying. I'm very new in the area and GSoC isn't a requirement. As I'm going to dedicate +500 hours into it, I may be able to help with other projects or tasks. Do you guys recommend any specific way to learn more about FOSSI and the projects under it?
Nitish-byte
@Nitish-byte
Hello @stevehoover , I have made the changes suggested by you in the proposal. Could you please review it again and give the feedback.
Kartikey rai
@kartikeyrai-me
Respected @stevehoover and @Jbalkind, I have made changes to my draft proposal for Integration of WARP-V with OpenPiton suggested by you.. Can you please review it and share the feedback.
Thank you!
Shahzaib Kashif
@shahzaibk23
Hi @stevehoover , hope you have reviewed my draft proposal for the project, Block Based Circuit Design. Shall I submit the Final Proposal then?
1 reply
Anjani K shukla
@skanjani
I think there could be many proposals for a project and mentors may have mentoring two or more projects. So I request students to have little patience. It may not possible to have multiple round of feedback for each proposal when mentors also have an regular job. Don't feel nervous, GSoC intention is to just involve students to get them experience of real world projects. Relax and focus on learning from their respective open source community. Best of luck to all!