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Zeeshan Rafique
@zeeshanrafique23
Ok, thanks.
MJVARMA
@MJVARMA
Hello everyone my name is MJ Varma, from India. I am currently pursuing my degree in Electronics and communication. I have basic knowledge on verilog and FPGA design and want to amplify that using this oppurtunity. I just started the course "Building a RISC-v CPU Core" to get my pre requistes on the project I want to work on. I have completed a course on IC physical Design which got more interested in this topic.
Can someone help me how do I get started?
MJVARMA
@MJVARMA
I want to contribute to this project "WARP-V TensorCore Extension for Deep Learning" because it meets only some part of my skill set and I can learn more things on my way
Theodore Omtzigt
@Ravenwater
@MJVARMA Great to hear you are interested in the TensorCore project. There are a handful of different angles we can take depending on your interest and skill level.
Kartikey rai
@kartikeyrai-me
Hello everyone, my name is Kartikey, and I am from India. I am currently a Pre - Final year student at Bennett University, and is pursuing my degree in Electronics and Communication Engineering. In past, I have worked on designing RISC - V where I implemented entire RV32I instruction set along branch prediction core using Verilog as HDL and Xilinx Vivado. At the time when I am writing this message, I currently have around 1.5 years of coding in Verilog, and along with RISC - V core, I have worked on other projects using Verilog.
I wanted to contribute to this project "RISC-V core with AI Acceleration synthesizable with open source tools" because it meets part of my skill set and I can learn more things on my way.
Dan Gisselquist
@ZipCPU
Welcome, Kaptain-99!
Kruti Deepan Panda
@krutideepanpanda
Hello everyone, I am Kruti. I am a 2nd year ECE student. I have basic knowledge of Verilog and have made a simple microprocessor. I am very much interested in learning more about RISC-V, especially on the project Idea "Compressed instruction support for SERV". I would like to contribute to it whether or not I get GSoC.
Anjani K shukla
@skanjani
nice spirit @krutideepanpanda! I hope that you will get selected.
Hello Everyone, I am Anjani, a pre-final year student at SATI India. I am preparing for the "Logical Equivalence Checks with LLHD" project as a GSoC student. I hope I will make some good friends here from FOSSi and librecores community.
I successfully build the CIRCT project and start searching for good first issue to take on before the application deadline.
Nitish-byte
@Nitish-byte
Hello everyone, I'm Nitish, a final year Electronics and telecommunication student at SPIT. I was interested in block-based circuit diagram. How should I start working on my proposal, any ideas?
Anjani K shukla
@skanjani
Hi @Nitish-byte! Looking at description of project it seems you must familiar with TL-Verilog, If you are not please visit their website and complete a tutorial. You should also familiar with MIT Scratch project. You should try to build the project and fix one or two issue. It may give some confidence to you. Also gives a better impression in you project proposal. All the scratch projects are under LLK organization on GitHub. See the link- https://github.com/LLK. Then you should also make yourself familiar with Google Blocky project. I see there is also a blocky-sample project under the same google organization. You might want to try a few example. Again fixing some minor issues from Blocky project will surely give a bright impression on your prospective mentors. Good luck for application!
Usman Zain
@usmnzen_twitter

Hello, I'm Usman, a final year computer science undergrad. I have designed a risc v 5 stage pipelined core, implementing the rv32i instruction set to get an idea of the opensource hardware. Currently, i am working on a software development kit that will program our SoC that @zeeshanrafique23 is leading.

I would like to like work on projects in the software domain that we can take as part of gsoc2021, if anyone is interested or has any ideas, please discuss. Thanks

Zeeshan Rafique
@zeeshanrafique23
Nice to see you here. @usmnzen_twitter
Steve Hoover
@stevehoover
Sorry for the delayed response, @Nitish-byte . I thought Dr. Mheta would reply, but she doesn't seem to be on Gitter. I've pinged her. Thanks, @skanjani for an on-point response to Nitish.
Anjani K shukla
@skanjani
NP @stevehoover, I am always happy to help new comers.
Nitish-byte
@Nitish-byte
Thank you @skanjani for the response, I'll start working on points that you've suggested. It's fine @stevehoover I just wanted the general idea on how to start working.
2019moaazkhaled
@2019moaazkhaled

Hi, I am moaaz, a senior student in nano-electronics department,
I have a good experience in Verilog and VHDL for both FPGA and ASIC flows. with a one year freelancing in the field of digital VLSI.

I want to participate in one of the projects propossed by FOSSI foundation in GSOC this year,
But I don't know how to communicate with the mentor !!!!

can anyone help me ?

2 replies
Shahzaib Kashif
@shahzaibk23

Hi, I am Shahzaib, a 3rd year Software Engineering Student. I have 2 years experience of working with HDLs and RISC-V ISA.

I am interested in working on Block Based Circuit Designing Project. Is anyone else also writing a proposal for that?

1 reply
2019moaazkhaled
@2019moaazkhaled
I wounder if it is available to participate in a project with a team of my colleges or not ?
1 reply
Shahzaib Kashif
@shahzaibk23

Hi, I am interested in working on Block Based Circuit Design Project.

I have submitted the draft proposal for that.
@gmehta_gitlab @stevehoover

Kindly review my proposal, all kinds of recommendations and suggestions are appreciated.

1 reply
2019moaazkhaled
@2019moaazkhaled
now I will start writing my proposals for two projects, I have just three days,
could any one help me with some tips?
Adithya Sunil
@adithyasunil26
Hello, I am Adithya Sunil and I am a 2nd-year Electronics and Communication Engineering student at IIIT Hyderabad. I have previously worked with verilog for various projects and assignments and I have some experience working with ISAs. I found the project idea for porting the BaseJump STL to FuseSoC quite interesting and I have submitted a draft proposal for the project. It would be very helpful to me if my proposal can be reviewed by a mentor so I can use the feedback to fix the shortcomings.
Thank you!
Nitish-byte
@Nitish-byte
Hello @stevehoover & @gmehta_gitlab , I have shared my draft proposal for block based circuit design, could you please review it and share the feedback.
Kartikey rai
@kartikeyrai-me
Respected @stevehoover and @Jbalkind, I have shared my draft proposal for Integration of WARP-V with OpenPiton via mail. Can you please review it and share the feedback.
Thank you!
Steve Hoover
@stevehoover
Will do, guys.
Elisa Silva
@minifyit_twitter
Hello everyone!
Elisa Silva
@minifyit_twitter
I'm brazilian C.S. student looking for a final project that involving Verilog and RISC-V. I'm got very interested in the project proposed by @olofk but looks like other people that have more experience in the topic are applying. I'm very new in the area and GSoC isn't a requirement. As I'm going to dedicate +500 hours into it, I may be able to help with other projects or tasks. Do you guys recommend any specific way to learn more about FOSSI and the projects under it?
Nitish-byte
@Nitish-byte
Hello @stevehoover , I have made the changes suggested by you in the proposal. Could you please review it again and give the feedback.
Kartikey rai
@kartikeyrai-me
Respected @stevehoover and @Jbalkind, I have made changes to my draft proposal for Integration of WARP-V with OpenPiton suggested by you.. Can you please review it and share the feedback.
Thank you!
Shahzaib Kashif
@shahzaibk23
Hi @stevehoover , hope you have reviewed my draft proposal for the project, Block Based Circuit Design. Shall I submit the Final Proposal then?
1 reply
Anjani K shukla
@skanjani
I think there could be many proposals for a project and mentors may have mentoring two or more projects. So I request students to have little patience. It may not possible to have multiple round of feedback for each proposal when mentors also have an regular job. Don't feel nervous, GSoC intention is to just involve students to get them experience of real world projects. Relax and focus on learning from their respective open source community. Best of luck to all!
KinzaQamar
@KinzaQamar
@olofk I have submitted my proposal related to adding "C" extension into SERV core.Kindly review that. Thank you
Sivaprasad S
@sivaprasad2000
@Jbalkind Can you review my draft proposal? I have submitted it on the GSoC platform
2019moaazkhaled
@2019moaazkhaled
hello, I have submitted a proposal for Bring up CV32E40P AI accelerator on FPGA project ,
@jeremybennett can you please give me a feedback.
Olof Kindgren
@olofk
It's great to see so many people interested in GSoC this year. I just wanted to mention again that SymbiFlow are also in GSoC this year and have projects around open source silicon and EDA. Make sure to check out what they have too https://symbiflow.github.io/
MOHIT GUPTA
@192215

Hello @stevehoover @Jbalkind @olofk @jeremybennett, I want to work on BeagleConnect - Low-Power Wide Area Networking Project because I am familiar with GPIO, ADC Drivers, and C language.

So, can you please suggest to me how do I contribute to this repository.

shivampotdar
@shivampotdar:matrix.org
[m]
Hey Mohit. Looks like there's some confusion here. This room is meant for Free and Open Source Silicon Foundation (FOSSi) and not Beagleboard.org
MOHIT GUPTA
@192215
Okay, it was sent there by mistake
Thanks @shivampotdar:matrix.org
MOHIT GUPTA
@192215
Hey, I would like to work on Extend LibreCores.org project bakened by PHP can anyone suggest me.
Ninad Jangle
@ninja3011
Hello! @stevehoover @gmehta_gitlab, I have submitted my final proposal for the Block-Based Circuit Design Project. I will continue to work on it. Thank you for your guidance over this process.
1 reply
Ninad Jangle
@ninja3011

This is my proposal (for Block-Based Circuit Design):

https://docs.google.com/document/d/1Yw-ev21OjIP2N2BFkQAuZLkw1uES4sqoQdoFnTNW_RQ/edit?usp=sharing

If anyone has any feedback or ideas they want to discuss, hmu!

Olof Kindgren
@olofk
Don't miss that FOSSi Dial-Up will resume on Tuesday https://www.fossi-foundation.org/dial-up/
Nitish-byte
@Nitish-byte
Hey @ninja3011 you're from VJTI college right.... I'm from SPIT. You're studying in which year? About the project I have started working on developing some basic custom blocks like adders, multipliers, etc. which can be useful for integrating it in circuit flows. I would like to know your approach and ideas on this project too !!!
Zeeshan Rafique
@zeeshanrafique23

Don't miss that FOSSi Dial-Up will resume on Tuesday https://www.fossi-foundation.org/dial-up/

That's great, thanks for letting us know.

Ninad Jangle
@ninja3011
@Nitish-byte Yeah! I am in Second Year. Right now, my finals are on. Can I contact you post 3rd march? I would love to compare and share approaches. Just before the finals, I was reading up on the specs of TL Verilog on tlx trying to brainstorm ways of implementations in JS.
Nitish-byte
@Nitish-byte
@ninja3011 Yeah sure!!! You mean post 3rd May right...
Ninad Jangle
@ninja3011
Yeah May*