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  • Jun 01 02:37
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  • Feb 26 11:34
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Anjani K shukla
@skanjani
nice spirit @krutideepanpanda! I hope that you will get selected.
Hello Everyone, I am Anjani, a pre-final year student at SATI India. I am preparing for the "Logical Equivalence Checks with LLHD" project as a GSoC student. I hope I will make some good friends here from FOSSi and librecores community.
I successfully build the CIRCT project and start searching for good first issue to take on before the application deadline.
Nitish-byte
@Nitish-byte
Hello everyone, I'm Nitish, a final year Electronics and telecommunication student at SPIT. I was interested in block-based circuit diagram. How should I start working on my proposal, any ideas?
Anjani K shukla
@skanjani
Hi @Nitish-byte! Looking at description of project it seems you must familiar with TL-Verilog, If you are not please visit their website and complete a tutorial. You should also familiar with MIT Scratch project. You should try to build the project and fix one or two issue. It may give some confidence to you. Also gives a better impression in you project proposal. All the scratch projects are under LLK organization on GitHub. See the link- https://github.com/LLK. Then you should also make yourself familiar with Google Blocky project. I see there is also a blocky-sample project under the same google organization. You might want to try a few example. Again fixing some minor issues from Blocky project will surely give a bright impression on your prospective mentors. Good luck for application!
Usman Zain
@usmnzen_twitter

Hello, I'm Usman, a final year computer science undergrad. I have designed a risc v 5 stage pipelined core, implementing the rv32i instruction set to get an idea of the opensource hardware. Currently, i am working on a software development kit that will program our SoC that @zeeshanrafique23 is leading.

I would like to like work on projects in the software domain that we can take as part of gsoc2021, if anyone is interested or has any ideas, please discuss. Thanks

Zeeshan Rafique
@zeeshanrafique23
Nice to see you here. @usmnzen_twitter
Steve Hoover
@stevehoover
Sorry for the delayed response, @Nitish-byte . I thought Dr. Mheta would reply, but she doesn't seem to be on Gitter. I've pinged her. Thanks, @skanjani for an on-point response to Nitish.
Anjani K shukla
@skanjani
NP @stevehoover, I am always happy to help new comers.
Nitish-byte
@Nitish-byte
Thank you @skanjani for the response, I'll start working on points that you've suggested. It's fine @stevehoover I just wanted the general idea on how to start working.
2019moaazkhaled
@2019moaazkhaled

Hi, I am moaaz, a senior student in nano-electronics department,
I have a good experience in Verilog and VHDL for both FPGA and ASIC flows. with a one year freelancing in the field of digital VLSI.

I want to participate in one of the projects propossed by FOSSI foundation in GSOC this year,
But I don't know how to communicate with the mentor !!!!

can anyone help me ?

2 replies
Shahzaib Kashif
@shahzaibk23

Hi, I am Shahzaib, a 3rd year Software Engineering Student. I have 2 years experience of working with HDLs and RISC-V ISA.

I am interested in working on Block Based Circuit Designing Project. Is anyone else also writing a proposal for that?

1 reply
2019moaazkhaled
@2019moaazkhaled
I wounder if it is available to participate in a project with a team of my colleges or not ?
1 reply
Shahzaib Kashif
@shahzaibk23

Hi, I am interested in working on Block Based Circuit Design Project.

I have submitted the draft proposal for that.
@gmehta_gitlab @stevehoover

Kindly review my proposal, all kinds of recommendations and suggestions are appreciated.

1 reply
2019moaazkhaled
@2019moaazkhaled
now I will start writing my proposals for two projects, I have just three days,
could any one help me with some tips?
Adithya Sunil
@adithyasunil26
Hello, I am Adithya Sunil and I am a 2nd-year Electronics and Communication Engineering student at IIIT Hyderabad. I have previously worked with verilog for various projects and assignments and I have some experience working with ISAs. I found the project idea for porting the BaseJump STL to FuseSoC quite interesting and I have submitted a draft proposal for the project. It would be very helpful to me if my proposal can be reviewed by a mentor so I can use the feedback to fix the shortcomings.
Thank you!
Nitish-byte
@Nitish-byte
Hello @stevehoover & @gmehta_gitlab , I have shared my draft proposal for block based circuit design, could you please review it and share the feedback.
Kartikey rai
@kartikeyrai-me
Respected @stevehoover and @Jbalkind, I have shared my draft proposal for Integration of WARP-V with OpenPiton via mail. Can you please review it and share the feedback.
Thank you!
Steve Hoover
@stevehoover
Will do, guys.
Elisa Silva
@minifyit_twitter
Hello everyone!
Elisa Silva
@minifyit_twitter
I'm brazilian C.S. student looking for a final project that involving Verilog and RISC-V. I'm got very interested in the project proposed by @olofk but looks like other people that have more experience in the topic are applying. I'm very new in the area and GSoC isn't a requirement. As I'm going to dedicate +500 hours into it, I may be able to help with other projects or tasks. Do you guys recommend any specific way to learn more about FOSSI and the projects under it?
Nitish-byte
@Nitish-byte
Hello @stevehoover , I have made the changes suggested by you in the proposal. Could you please review it again and give the feedback.
Kartikey rai
@kartikeyrai-me
Respected @stevehoover and @Jbalkind, I have made changes to my draft proposal for Integration of WARP-V with OpenPiton suggested by you.. Can you please review it and share the feedback.
Thank you!
Shahzaib Kashif
@shahzaibk23
Hi @stevehoover , hope you have reviewed my draft proposal for the project, Block Based Circuit Design. Shall I submit the Final Proposal then?
1 reply
Anjani K shukla
@skanjani
I think there could be many proposals for a project and mentors may have mentoring two or more projects. So I request students to have little patience. It may not possible to have multiple round of feedback for each proposal when mentors also have an regular job. Don't feel nervous, GSoC intention is to just involve students to get them experience of real world projects. Relax and focus on learning from their respective open source community. Best of luck to all!
KinzaQamar
@KinzaQamar
@olofk I have submitted my proposal related to adding "C" extension into SERV core.Kindly review that. Thank you
Sivaprasad S
@sivaprasad2000
@Jbalkind Can you review my draft proposal? I have submitted it on the GSoC platform
2019moaazkhaled
@2019moaazkhaled
hello, I have submitted a proposal for Bring up CV32E40P AI accelerator on FPGA project ,
@jeremybennett can you please give me a feedback.
Olof Kindgren
@olofk
It's great to see so many people interested in GSoC this year. I just wanted to mention again that SymbiFlow are also in GSoC this year and have projects around open source silicon and EDA. Make sure to check out what they have too https://symbiflow.github.io/
MOHIT GUPTA
@192215

Hello @stevehoover @Jbalkind @olofk @jeremybennett, I want to work on BeagleConnect - Low-Power Wide Area Networking Project because I am familiar with GPIO, ADC Drivers, and C language.

So, can you please suggest to me how do I contribute to this repository.

shivampotdar
@shivampotdar:matrix.org
[m]
Hey Mohit. Looks like there's some confusion here. This room is meant for Free and Open Source Silicon Foundation (FOSSi) and not Beagleboard.org
MOHIT GUPTA
@192215
Okay, it was sent there by mistake
Thanks @shivampotdar:matrix.org
MOHIT GUPTA
@192215
Hey, I would like to work on Extend LibreCores.org project bakened by PHP can anyone suggest me.
Ninad Jangle
@ninja3011
Hello! @stevehoover @gmehta_gitlab, I have submitted my final proposal for the Block-Based Circuit Design Project. I will continue to work on it. Thank you for your guidance over this process.
1 reply
Ninad Jangle
@ninja3011

This is my proposal (for Block-Based Circuit Design):

https://docs.google.com/document/d/1Yw-ev21OjIP2N2BFkQAuZLkw1uES4sqoQdoFnTNW_RQ/edit?usp=sharing

If anyone has any feedback or ideas they want to discuss, hmu!

Olof Kindgren
@olofk
Don't miss that FOSSi Dial-Up will resume on Tuesday https://www.fossi-foundation.org/dial-up/
Nitish-byte
@Nitish-byte
Hey @ninja3011 you're from VJTI college right.... I'm from SPIT. You're studying in which year? About the project I have started working on developing some basic custom blocks like adders, multipliers, etc. which can be useful for integrating it in circuit flows. I would like to know your approach and ideas on this project too !!!
Zeeshan Rafique
@zeeshanrafique23

Don't miss that FOSSi Dial-Up will resume on Tuesday https://www.fossi-foundation.org/dial-up/

That's great, thanks for letting us know.

Ninad Jangle
@ninja3011
@Nitish-byte Yeah! I am in Second Year. Right now, my finals are on. Can I contact you post 3rd march? I would love to compare and share approaches. Just before the finals, I was reading up on the specs of TL Verilog on tlx trying to brainstorm ways of implementations in JS.
Nitish-byte
@Nitish-byte
@ninja3011 Yeah sure!!! You mean post 3rd May right...
Ninad Jangle
@ninja3011
Yeah May*
Ninad Jangle
@ninja3011

Today I got a bit of time to work on blocky again, I was looking at the generators that come fully built into blocky, mainly javascript.js. It seems the closest to ours compared to lua or python.

Most of our logical ops will use similar code. I think we can need to have a complete list of keywords in TL-Verilog, I have not been able to find one till now. It can be compiled if not there.

https://github.com/google/blockly/blob/master/generators/javascript.js

There are a lot more things that get added with further documentation but I feel 1a itself provides a solid foundation to build a base generator.

https://docs.google.com/document/d/19wJ1jzm5gvQE_tP-rFZLs8Sj-TNZRaeC-mDVyqGp3-g/pub

@Nitish-byte check out the generator and specs sheet and let me know if you feel similarly.

1 reply
Ninad Jangle
@ninja3011
@stevehoover, thank you! , the specs seem like the docs I have been reading. I'll keep the reference card at hand while coding, it will be helpful.
I have gone through the tutorials, but ill do a quick revision again.
Ninad Jangle
@ninja3011
I had my assignment week and finals in the last 2 weeks, so I was not able to do major work till now. I will be able to dive into the heavy work from tomorrow ( finals ending )
Nitish-byte
@Nitish-byte
Hey @ninja3011 thanks for the update I read the documents sent by you, how was your exam? Actually currently I'm busy with my final year evaluations which will end on 12th May. Hopefully I could dedicate much of my time on this after that. About these documents, I didn't exactly understand the correlation with the generator code for javascript, could you elaborate on that? @stevehoover thanks for the reference. @ninja3011 I'll till then try to implement some flows using the algorithms in makerchip tutorials and your HDL doc too was helpful and gave me some idea.
Ninad Jangle
@ninja3011
@Nitish-byte Best of luck with your evaluations! The exams went well, our practical exams are this week so I am working on blocky part-time now till 14th as well. About the docs, the idea was to know concisely what elements are needed to be a part of the generator. By learning TL Verilog we start with the stuff we are familiar with, but having a compiled list acts as a double-check for all elements. But yes, as our main aim is to convert to TLV, how the instructions work from there isn't crucial to our proj, but still good to know.
mayank-kabra2001
@mayank-kabra2001
Kudos ! to everyone who got selected for gsoc 2021 :)
shivampotdar
@shivampotdar:matrix.org
[m]
Congrats to all students and FOSSi for a good number of selections this year too!
Aquib Baig
@aquibbaig
Congratulations on getting selected for gsoc 2021 and all the best!
Nazerke Turtayeva
@NazerkeT

Thanks for the congratulations! Happy to share that my proposal has been accepted this year! I will be working on Multi-level TLB enhancement for Ariane in OpenPiton.

Wish good luck to all GSoC'21 participants and open-source enthusiasts!