This is my proposal (for Block-Based Circuit Design):
https://docs.google.com/document/d/1Yw-ev21OjIP2N2BFkQAuZLkw1uES4sqoQdoFnTNW_RQ/edit?usp=sharing
If anyone has any feedback or ideas they want to discuss, hmu!
Don't miss that FOSSi Dial-Up will resume on Tuesday https://www.fossi-foundation.org/dial-up/
That's great, thanks for letting us know.
Today I got a bit of time to work on blocky again, I was looking at the generators that come fully built into blocky, mainly javascript.js. It seems the closest to ours compared to lua or python.
Most of our logical ops will use similar code. I think we can need to have a complete list of keywords in TL-Verilog, I have not been able to find one till now. It can be compiled if not there.
https://github.com/google/blockly/blob/master/generators/javascript.js
There are a lot more things that get added with further documentation but I feel 1a itself provides a solid foundation to build a base generator.
https://docs.google.com/document/d/19wJ1jzm5gvQE_tP-rFZLs8Sj-TNZRaeC-mDVyqGp3-g/pub
@Nitish-byte check out the generator and specs sheet and let me know if you feel similarly.
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Hi all,
I'd like to announce recently update of my project "RgGen".
https://github.com/rggen/rggen
I've published the first release of VHDL plugin for RgGen.
https://github.com/rggen/rggen-vhdl
By using RgGen and this plugin, you can generate CSR modules written in VHDL from human readable register map specifications.
Sample register map:
https://github.com/rggen/rggen-sample/blob/master/block_0.yml
https://github.com/rggen/rggen-sample/blob/master/block_0.rb
https://github.com/rggen/rggen-sample/blob/master/block_0.xlsx
Generated VHDL module
https://github.com/rggen/rggen-sample/blob/master/block_0.vhd
RgGen now supports all major HDL (SV/Verilog/VHDL) !
type misc_ctrl_t is record -- 32 bits
reset : std_logic; -- bit 31
nco_ctrl_word: std_logic_vector(30 downto 16);
accum_phase: unsigned(15 downto 0);
end record;std_logic/std_logic_vector instead of the unresolved std_ulogic/std_ulogic_vector. In addition, I rarely see boolean for signals nor do I see bit or bit_vector's. If you generate some register maps with AirHDL, hopefully it'll make more sense what most VHDL developers use
RgGen is 4th generation of my CSR automation tool and I started development of 1st generation about 10 years ago
No worries, I was just curious. I've seen a lot of tools like this and I'll be searching around for one eventually to automate some of my companies doc/develop process. However, likely we'll have to roll our own solution because our registers and register maps are not AXI and we have more complexity so the only thing we could leverage is doc generation I think.
both of std_logic_vector and unsigned types is defined as array of std_loigc.
unsigned data type has operators used with integer but std_logic_vector does not.
std_logic* is simply just a bit or bits of an enum U, X, 0, 1, Z, W, L, H, and - Reference. unsigned is defined in numeric_std. Anyways, using std_logic_vector and std_logic would be preferred for registers as it is the most intuitive. bits in unsigned are inherently related and I would not want a register generation tool to use that type unless I specifically told it to do so (e.g. for something like a cycle/bit counter, frequency, etc.)
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