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MOHIT GUPTA
@192215
Hey, I would like to work on Extend LibreCores.org project bakened by PHP can anyone suggest me.
Ninad S. Jangle
@ninja3011
Hello! @stevehoover @gmehta_gitlab, I have submitted my final proposal for the Block-Based Circuit Design Project. I will continue to work on it. Thank you for your guidance over this process.
1 reply
Ninad S. Jangle
@ninja3011

This is my proposal (for Block-Based Circuit Design):

https://docs.google.com/document/d/1Yw-ev21OjIP2N2BFkQAuZLkw1uES4sqoQdoFnTNW_RQ/edit?usp=sharing

If anyone has any feedback or ideas they want to discuss, hmu!

Olof Kindgren
@olofk
Don't miss that FOSSi Dial-Up will resume on Tuesday https://www.fossi-foundation.org/dial-up/
Nitish-byte
@Nitish-byte
Hey @ninja3011 you're from VJTI college right.... I'm from SPIT. You're studying in which year? About the project I have started working on developing some basic custom blocks like adders, multipliers, etc. which can be useful for integrating it in circuit flows. I would like to know your approach and ideas on this project too !!!
Zeeshan Rafique
@zeeshanrafique23

Don't miss that FOSSi Dial-Up will resume on Tuesday https://www.fossi-foundation.org/dial-up/

That's great, thanks for letting us know.

Ninad S. Jangle
@ninja3011
@Nitish-byte Yeah! I am in Second Year. Right now, my finals are on. Can I contact you post 3rd march? I would love to compare and share approaches. Just before the finals, I was reading up on the specs of TL Verilog on tlx trying to brainstorm ways of implementations in JS.
Nitish-byte
@Nitish-byte
@ninja3011 Yeah sure!!! You mean post 3rd May right...
Ninad S. Jangle
@ninja3011
Yeah May*
Ninad S. Jangle
@ninja3011

Today I got a bit of time to work on blocky again, I was looking at the generators that come fully built into blocky, mainly javascript.js. It seems the closest to ours compared to lua or python.

Most of our logical ops will use similar code. I think we can need to have a complete list of keywords in TL-Verilog, I have not been able to find one till now. It can be compiled if not there.

https://github.com/google/blockly/blob/master/generators/javascript.js

There are a lot more things that get added with further documentation but I feel 1a itself provides a solid foundation to build a base generator.

https://docs.google.com/document/d/19wJ1jzm5gvQE_tP-rFZLs8Sj-TNZRaeC-mDVyqGp3-g/pub

@Nitish-byte check out the generator and specs sheet and let me know if you feel similarly.

1 reply
Ninad S. Jangle
@ninja3011
@stevehoover, thank you! , the specs seem like the docs I have been reading. I'll keep the reference card at hand while coding, it will be helpful.
I have gone through the tutorials, but ill do a quick revision again.
Ninad S. Jangle
@ninja3011
I had my assignment week and finals in the last 2 weeks, so I was not able to do major work till now. I will be able to dive into the heavy work from tomorrow ( finals ending )
Nitish-byte
@Nitish-byte
Hey @ninja3011 thanks for the update I read the documents sent by you, how was your exam? Actually currently I'm busy with my final year evaluations which will end on 12th May. Hopefully I could dedicate much of my time on this after that. About these documents, I didn't exactly understand the correlation with the generator code for javascript, could you elaborate on that? @stevehoover thanks for the reference. @ninja3011 I'll till then try to implement some flows using the algorithms in makerchip tutorials and your HDL doc too was helpful and gave me some idea.
Ninad S. Jangle
@ninja3011
@Nitish-byte Best of luck with your evaluations! The exams went well, our practical exams are this week so I am working on blocky part-time now till 14th as well. About the docs, the idea was to know concisely what elements are needed to be a part of the generator. By learning TL Verilog we start with the stuff we are familiar with, but having a compiled list acts as a double-check for all elements. But yes, as our main aim is to convert to TLV, how the instructions work from there isn't crucial to our proj, but still good to know.
mayank-kabra2001
@mayank-kabra2001
Kudos ! to everyone who got selected for gsoc 2021 :)
shivampotdar
@shivampotdar:matrix.org
[m]
Congrats to all students and FOSSi for a good number of selections this year too!
Aquib Baig
@aquibbaig
Congratulations on getting selected for gsoc 2021 and all the best!
Nazerke Turtayeva
@NazerkeT

Thanks for the congratulations! Happy to share that my proposal has been accepted this year! I will be working on Multi-level TLB enhancement for Ariane in OpenPiton.

Wish good luck to all GSoC'21 participants and open-source enthusiasts!

2019moaazkhaled
@2019moaazkhaled

congratulation for all the accepted students,
unfortunately I was not accepted.

my proposal was on Bring up CV32E40P AI accelerator on FPGA
can I have a contact to the one who was chosen?

Priyanshu Mishra
@Priyans57411485_twitter
Good luck to all the GSoC'21.
Deepak S
@Deepak-suresh14
Kudos! to all who got selected :)
Taichi Ishitani
@taichi-ishitani

Hi all,
I'd like to announce recently update of my project "RgGen".
https://github.com/rggen/rggen

I've published the first release of VHDL plugin for RgGen.
https://github.com/rggen/rggen-vhdl
By using RgGen and this plugin, you can generate CSR modules written in VHDL from human readable register map specifications.

Sample register map:
https://github.com/rggen/rggen-sample/blob/master/block_0.yml
https://github.com/rggen/rggen-sample/blob/master/block_0.rb
https://github.com/rggen/rggen-sample/blob/master/block_0.xlsx
Generated VHDL module
https://github.com/rggen/rggen-sample/blob/master/block_0.vhd

RgGen now supports all major HDL (SV/Verilog/VHDL) !

Olof Kindgren
@olofk
Thanks @taichi-ishitani . Does it support SystemRDL as the input format?
Taichi Ishitani
@taichi-ishitani
currently no.
I'm implementing SystemRDL parser now
Taichi Ishitani
@taichi-ishitani
Is SystemRDL support an important feature?
In Japan, SystemRDL is not popular format so I'm not sure its importance.
Jonathan Balkind
@Jbalkind
I'm glad to see more releases @taichi-ishitani ! Excellent work :D
GlenNicholls
@GlenNicholls
@taichi-ishitani Have you seen AirHDL, tsfpga, and cheby? Just curious becaues I've been seeing a lot of duplication of effort with similar OS tools. AirHDL isn't open source and only certain features are free, but I am curious why you decided to start a new tool. Is there something that yours solves that others don't?
Olof Kindgren
@olofk
@taichi-ishitani Sou desu ka. I'm not sure how SystemRDL is in other parts of the world but since there is already some good open source tooling for working with SystemRDL I think it is currently in the best position to become the standard format for describing registers. I have moved to SystemRDL now for my latest designs
Jonathan Balkind
@Jbalkind
@GlenNicholls looks like those others started around the same time as rggen? It's at least two years old iirc
Olof Kindgren
@olofk
It's a problem that many people try to solve and I think it's great that we have several approaches and tools that suit different use cases. At the same time it would be fantastic to have interoperability between them somehow and I'm betting on SystemRDL as the Lingua Franca of registers
Taichi Ishitani
@taichi-ishitani
@GlenNicholls
I've seen airhdl but not seen tsfpga and cheby.
RgGen is 4th generation of my CSR automation tool and I started development of 1st generation about 10 years ago
Taichi Ishitani
@taichi-ishitani
@olofk ,
Thanks for your advice. I understand that RgGen should support SystemRDL.
Taichi Ishitani
@taichi-ishitani
RgGen has plugin feature, I think this is an advanced feature.
You can customize RgGen. For example
  • special register/bit field types
  • bus protocols other than APB and AXI4 Lite
  • your own input format
  • output file generation other than RTL, RAL and MD
Taichi Ishitani
@taichi-ishitani
VHDL experts:
I use mainly SystemVerilog so I'm not familiar with VHDL.
I'm confused because VHDL has a lot of data types.
Which should I use std_logic_vector or unsigned for bus signals?
GlenNicholls
@GlenNicholls
It depends on the bus signal. Personally, I would default to std_logic_vector as it is most portable. However, I looked through AirHDL's tabs and they also offer record ports (wraps many signals/types in something that looks like an enum):
type misc_ctrl_t is record -- 32 bits
    reset : std_logic;  -- bit 31
    nco_ctrl_word: std_logic_vector(30 downto 16);              
    accum_phase: unsigned(15 downto 0);
end record;
@taichi-ishitani can you point me to something you're wondering about? VHDL only has a few core types, but everyone I know and code I see online uses std_logic/std_logic_vector instead of the unresolved std_ulogic/std_ulogic_vector. In addition, I rarely see boolean for signals nor do I see bit or bit_vector's. If you generate some register maps with AirHDL, hopefully it'll make more sense what most VHDL developers use
Taichi Ishitani
@taichi-ishitani
both of std_logic_vector and unsigned types is defined as array of std_loigc.
unsigned data type has operators used with integer but std_logic_vector does not.
Taichi Ishitani
@taichi-ishitani
I often see std_logic_vector than unsinged.
Therefore, I ask this question.
GlenNicholls
@GlenNicholls

RgGen is 4th generation of my CSR automation tool and I started development of 1st generation about 10 years ago

No worries, I was just curious. I've seen a lot of tools like this and I'll be searching around for one eventually to automate some of my companies doc/develop process. However, likely we'll have to roll our own solution because our registers and register maps are not AXI and we have more complexity so the only thing we could leverage is doc generation I think.

both of std_logic_vector and unsigned types is defined as array of std_loigc.
unsigned data type has operators used with integer but std_logic_vector does not.

std_logic* is simply just a bit or bits of an enum U, X, 0, 1, Z, W, L, H, and - Reference. unsigned is defined in numeric_std. Anyways, using std_logic_vector and std_logic would be preferred for registers as it is the most intuitive. bits in unsigned are inherently related and I would not want a register generation tool to use that type unless I specifically told it to do so (e.g. for something like a cycle/bit counter, frequency, etc.)

1 reply
GlenNicholls
@GlenNicholls
Feel free to PM me or tag me in GitHub issues when you have questions about VHDL, I'm more than willing to code review or provide insight. Also https://gitter.im/vhdl/General is another good place to ask VHDL questions because I don't see as many VHDL users in here. Many people in that room maintain the VHDL standard and can answer questions when you experience difficulties with the type checking in VHDL as I know that it is a lot to digest at first
Taichi Ishitani
@taichi-ishitani

registers and register maps are not AXI

We also use non AXI bus protocol so we create our own plugin to support the bus protocol which we use.

we have more complexity

Do you need not only simple register/bit field types but also complex types?
If yes, what kind of types do you need?

GlenNicholls
@GlenNicholls

We also use non AXI bus protocol so we create our own plugin to support the bus protocol which we use.

interesting, I'll look into rggen more once I start experimenting with incorporating some of my ideas in our flow. It'd be a lifesaver if I didn't have to write something from scratch.

Do you need not only simple register/bit field types but also complex types?

Sort of, we also have an interesting interface to software. It's kind of hard to explain but works really nicely for coupling software and firmware. I'll PM you.

Taichi Ishitani
@taichi-ishitani

for something like a cycle/bit counter, frequency, etc

Signals defined as unsinged should show number and std_logic_vector is more general than unsigned.
Therefore, I should use std_logic_vector for register.
Is my understanding correct?

GlenNicholls
@GlenNicholls
Yes, you're understanding is correct. unsigned and signed are generally used specifically for manipulating numbers (like adding/subtracting). std_logic_vector are just bits (vector of std_logic) that may or may not have any relationship
Taichi Ishitani
@taichi-ishitani
Thank you!
Your help make my understanding more clearly.
GlenNicholls
@GlenNicholls
No problem! Again, feel free to tag me whenever you have any questions or want me to look at code.
Taichi Ishitani
@taichi-ishitani
Thank you!
Olof Kindgren
@olofk
Haha. I see you brought up my favorite pet peeve about VHDL. It's a fine language, especially since 2008 and onwards, but there are just so many VHDL users who likes to mention how good it is for type safety and then they still use std_logic instead of std_ulogic everywhere :)
TBF, std_logic was actually a different type from std_ulogic instead of a resolved subtype prior to vhdl2008 so you had to make explicit casts between them, but still