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2019moaazkhaled
@2019moaazkhaled

congratulation for all the accepted students,
unfortunately I was not accepted.

my proposal was on Bring up CV32E40P AI accelerator on FPGA
can I have a contact to the one who was chosen?

Priyanshu Mishra
@Priyans57411485_twitter
Good luck to all the GSoC'21.
Deepak S
@Deepak-suresh14
Kudos! to all who got selected :)
Taichi Ishitani
@taichi-ishitani

Hi all,
I'd like to announce recently update of my project "RgGen".
https://github.com/rggen/rggen

I've published the first release of VHDL plugin for RgGen.
https://github.com/rggen/rggen-vhdl
By using RgGen and this plugin, you can generate CSR modules written in VHDL from human readable register map specifications.

Sample register map:
https://github.com/rggen/rggen-sample/blob/master/block_0.yml
https://github.com/rggen/rggen-sample/blob/master/block_0.rb
https://github.com/rggen/rggen-sample/blob/master/block_0.xlsx
Generated VHDL module
https://github.com/rggen/rggen-sample/blob/master/block_0.vhd

RgGen now supports all major HDL (SV/Verilog/VHDL) !

Olof Kindgren
@olofk
Thanks @taichi-ishitani . Does it support SystemRDL as the input format?
Taichi Ishitani
@taichi-ishitani
currently no.
I'm implementing SystemRDL parser now
Taichi Ishitani
@taichi-ishitani
Is SystemRDL support an important feature?
In Japan, SystemRDL is not popular format so I'm not sure its importance.
Jonathan Balkind
@Jbalkind
I'm glad to see more releases @taichi-ishitani ! Excellent work :D
GlenNicholls
@GlenNicholls
@taichi-ishitani Have you seen AirHDL, tsfpga, and cheby? Just curious becaues I've been seeing a lot of duplication of effort with similar OS tools. AirHDL isn't open source and only certain features are free, but I am curious why you decided to start a new tool. Is there something that yours solves that others don't?
Olof Kindgren
@olofk
@taichi-ishitani Sou desu ka. I'm not sure how SystemRDL is in other parts of the world but since there is already some good open source tooling for working with SystemRDL I think it is currently in the best position to become the standard format for describing registers. I have moved to SystemRDL now for my latest designs
Jonathan Balkind
@Jbalkind
@GlenNicholls looks like those others started around the same time as rggen? It's at least two years old iirc
Olof Kindgren
@olofk
It's a problem that many people try to solve and I think it's great that we have several approaches and tools that suit different use cases. At the same time it would be fantastic to have interoperability between them somehow and I'm betting on SystemRDL as the Lingua Franca of registers
Taichi Ishitani
@taichi-ishitani
@GlenNicholls
I've seen airhdl but not seen tsfpga and cheby.
RgGen is 4th generation of my CSR automation tool and I started development of 1st generation about 10 years ago
Taichi Ishitani
@taichi-ishitani
@olofk ,
Thanks for your advice. I understand that RgGen should support SystemRDL.
Taichi Ishitani
@taichi-ishitani
RgGen has plugin feature, I think this is an advanced feature.
You can customize RgGen. For example
  • special register/bit field types
  • bus protocols other than APB and AXI4 Lite
  • your own input format
  • output file generation other than RTL, RAL and MD
Taichi Ishitani
@taichi-ishitani
VHDL experts:
I use mainly SystemVerilog so I'm not familiar with VHDL.
I'm confused because VHDL has a lot of data types.
Which should I use std_logic_vector or unsigned for bus signals?
GlenNicholls
@GlenNicholls
It depends on the bus signal. Personally, I would default to std_logic_vector as it is most portable. However, I looked through AirHDL's tabs and they also offer record ports (wraps many signals/types in something that looks like an enum):
type misc_ctrl_t is record -- 32 bits
    reset : std_logic;  -- bit 31
    nco_ctrl_word: std_logic_vector(30 downto 16);              
    accum_phase: unsigned(15 downto 0);
end record;
@taichi-ishitani can you point me to something you're wondering about? VHDL only has a few core types, but everyone I know and code I see online uses std_logic/std_logic_vector instead of the unresolved std_ulogic/std_ulogic_vector. In addition, I rarely see boolean for signals nor do I see bit or bit_vector's. If you generate some register maps with AirHDL, hopefully it'll make more sense what most VHDL developers use
Taichi Ishitani
@taichi-ishitani
both of std_logic_vector and unsigned types is defined as array of std_loigc.
unsigned data type has operators used with integer but std_logic_vector does not.
Taichi Ishitani
@taichi-ishitani
I often see std_logic_vector than unsinged.
Therefore, I ask this question.
GlenNicholls
@GlenNicholls

RgGen is 4th generation of my CSR automation tool and I started development of 1st generation about 10 years ago

No worries, I was just curious. I've seen a lot of tools like this and I'll be searching around for one eventually to automate some of my companies doc/develop process. However, likely we'll have to roll our own solution because our registers and register maps are not AXI and we have more complexity so the only thing we could leverage is doc generation I think.

both of std_logic_vector and unsigned types is defined as array of std_loigc.
unsigned data type has operators used with integer but std_logic_vector does not.

std_logic* is simply just a bit or bits of an enum U, X, 0, 1, Z, W, L, H, and - Reference. unsigned is defined in numeric_std. Anyways, using std_logic_vector and std_logic would be preferred for registers as it is the most intuitive. bits in unsigned are inherently related and I would not want a register generation tool to use that type unless I specifically told it to do so (e.g. for something like a cycle/bit counter, frequency, etc.)

1 reply
GlenNicholls
@GlenNicholls
Feel free to PM me or tag me in GitHub issues when you have questions about VHDL, I'm more than willing to code review or provide insight. Also https://gitter.im/vhdl/General is another good place to ask VHDL questions because I don't see as many VHDL users in here. Many people in that room maintain the VHDL standard and can answer questions when you experience difficulties with the type checking in VHDL as I know that it is a lot to digest at first
Taichi Ishitani
@taichi-ishitani

registers and register maps are not AXI

We also use non AXI bus protocol so we create our own plugin to support the bus protocol which we use.

we have more complexity

Do you need not only simple register/bit field types but also complex types?
If yes, what kind of types do you need?

GlenNicholls
@GlenNicholls

We also use non AXI bus protocol so we create our own plugin to support the bus protocol which we use.

interesting, I'll look into rggen more once I start experimenting with incorporating some of my ideas in our flow. It'd be a lifesaver if I didn't have to write something from scratch.

Do you need not only simple register/bit field types but also complex types?

Sort of, we also have an interesting interface to software. It's kind of hard to explain but works really nicely for coupling software and firmware. I'll PM you.

Taichi Ishitani
@taichi-ishitani

for something like a cycle/bit counter, frequency, etc

Signals defined as unsinged should show number and std_logic_vector is more general than unsigned.
Therefore, I should use std_logic_vector for register.
Is my understanding correct?

GlenNicholls
@GlenNicholls
Yes, you're understanding is correct. unsigned and signed are generally used specifically for manipulating numbers (like adding/subtracting). std_logic_vector are just bits (vector of std_logic) that may or may not have any relationship
Taichi Ishitani
@taichi-ishitani
Thank you!
Your help make my understanding more clearly.
GlenNicholls
@GlenNicholls
No problem! Again, feel free to tag me whenever you have any questions or want me to look at code.
Taichi Ishitani
@taichi-ishitani
Thank you!
Olof Kindgren
@olofk
Haha. I see you brought up my favorite pet peeve about VHDL. It's a fine language, especially since 2008 and onwards, but there are just so many VHDL users who likes to mention how good it is for type safety and then they still use std_logic instead of std_ulogic everywhere :)
TBF, std_logic was actually a different type from std_ulogic instead of a resolved subtype prior to vhdl2008 so you had to make explicit casts between them, but still
I think VHDL could be much more popular if VHDL users just stopped treating it as a very verbose verilog and actually started using the good stuff in the language
Taichi Ishitani
@taichi-ishitani
This is the first time to write VHDL.
Function overloading and type inference at calling function are interesting features. I want SystemVerilog to support these features!
Jeremy Bennett
@jeremybennett
Welcome @veronia-iskandar a PhD student at TU Dresden, who is working with me and Will Jones on a FOSSi Google Summer of Code project to advance the work done by Southampton Uni on adding AI support to the CV32E40P.
Zeeshan Rafique
@zeeshanrafique23
Sounds interesting, Welcome @veronia-iskandar
Stafford Horne
@stffrdhrn
@taichi-ishitani cool, project. I live in Japan too, its always to to see other local interest in open source hardware.
Dan Gisselquist
@ZipCPU
taichi-ishitani: Do you have any examples of register logic created by your tool? I'd love to take a look.
Stafford Horne
@stffrdhrn
@ZipCPU , meet @Harshitha172000 , I am mentoring her for Gsoc this year doing formal verification of the mor1x cpu. Thanks again for your comments on her latest blog entry https://harshitha172000.github.io/blog2.html
Taichi Ishitani
@taichi-ishitani
@stffrdhrn ,
Thank you!
I'm developing UVM based AXI VIP and NoC router written in SytemVerilog.
These are also open source.
@ZipCPU ,
You can find sample RTL and others from this repository.
https://github.com/rggen/rggen-sample
Dan Gisselquist
@ZipCPU
*examinse
*examines
Taichi Ishitani
@taichi-ishitani
These are repositories for common RLT modules. Generated RTL modules are constructed with these common modules.
Dan Gisselquist
@ZipCPU
taichi-ishitani: Have you considered this AXI requirement: https://github.com/ZipCPU/website/blob/master/img/tweets/axi-spec-registered.png ?
2 replies
It looks like your READY signals are built combinatorially off of the AXI VALID signals, which would violate this criteria.
Am I missing something?
Dan Gisselquist
@ZipCPU
Also, what happens if AWVALID shows up first? It looks like AWREADY will be set, after which AWVALID (may) be dropped. If WVALID then shows up, get_request_valid will never notice since both AWVALID and WVALID won't be true on the same cycle.
2 replies