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  • Oct 05 23:44
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  • Jun 05 09:20
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GlenNicholls
@GlenNicholls
Yes, you're understanding is correct. unsigned and signed are generally used specifically for manipulating numbers (like adding/subtracting). std_logic_vector are just bits (vector of std_logic) that may or may not have any relationship
Taichi Ishitani
@taichi-ishitani
Thank you!
Your help make my understanding more clearly.
GlenNicholls
@GlenNicholls
No problem! Again, feel free to tag me whenever you have any questions or want me to look at code.
Taichi Ishitani
@taichi-ishitani
Thank you!
Olof Kindgren
@olofk
Haha. I see you brought up my favorite pet peeve about VHDL. It's a fine language, especially since 2008 and onwards, but there are just so many VHDL users who likes to mention how good it is for type safety and then they still use std_logic instead of std_ulogic everywhere :)
TBF, std_logic was actually a different type from std_ulogic instead of a resolved subtype prior to vhdl2008 so you had to make explicit casts between them, but still
I think VHDL could be much more popular if VHDL users just stopped treating it as a very verbose verilog and actually started using the good stuff in the language
Taichi Ishitani
@taichi-ishitani
This is the first time to write VHDL.
Function overloading and type inference at calling function are interesting features. I want SystemVerilog to support these features!
Jeremy Bennett
@jeremybennett
Welcome @veronia-iskandar a PhD student at TU Dresden, who is working with me and Will Jones on a FOSSi Google Summer of Code project to advance the work done by Southampton Uni on adding AI support to the CV32E40P.
Zeeshan Rafique
@zeeshanrafique23
Sounds interesting, Welcome @veronia-iskandar
Stafford Horne
@stffrdhrn
@taichi-ishitani cool, project. I live in Japan too, its always to to see other local interest in open source hardware.
Dan Gisselquist
@ZipCPU
taichi-ishitani: Do you have any examples of register logic created by your tool? I'd love to take a look.
Stafford Horne
@stffrdhrn
@ZipCPU , meet @Harshitha172000 , I am mentoring her for Gsoc this year doing formal verification of the mor1x cpu. Thanks again for your comments on her latest blog entry https://harshitha172000.github.io/blog2.html
Taichi Ishitani
@taichi-ishitani
@stffrdhrn ,
Thank you!
I'm developing UVM based AXI VIP and NoC router written in SytemVerilog.
These are also open source.
@ZipCPU ,
You can find sample RTL and others from this repository.
https://github.com/rggen/rggen-sample
Dan Gisselquist
@ZipCPU
*examinse
*examines
Taichi Ishitani
@taichi-ishitani
These are repositories for common RLT modules. Generated RTL modules are constructed with these common modules.
Dan Gisselquist
@ZipCPU
taichi-ishitani: Have you considered this AXI requirement: https://github.com/ZipCPU/website/blob/master/img/tweets/axi-spec-registered.png ?
2 replies
It looks like your READY signals are built combinatorially off of the AXI VALID signals, which would violate this criteria.
Am I missing something?
Dan Gisselquist
@ZipCPU
Also, what happens if AWVALID shows up first? It looks like AWREADY will be set, after which AWVALID (may) be dropped. If WVALID then shows up, get_request_valid will never notice since both AWVALID and WVALID won't be true on the same cycle.
2 replies
Dan Gisselquist
@ZipCPU
Let me recommend this article on skid buffers to you--it's the easiest way to fix the combinatorial issue: https://zipcpu.com/blog/2019/05/22/skidbuffer.html
1) AXI4-lite doesn't have ID's. AXI5-lite does. 2) If AW shows up before W, then you don't want to process the write. In that case, you might grab the wrong ID.
Either way, cheers, and I'm glad I was able to help.
Dan Gisselquist
@ZipCPU
Ahh, okay -- but that's something you'll need to fix for the other reason. Still, that part at least makes more sense now.
Here's the logic I typically use in my register write logic: https://github.com/ZipCPU/wb2axip/blob/master/rtl/easyaxil.v#L151-L152
It works, but only if it follows a skid buffer.
I'm also known for keeping the read and write paths of the AXI interface separate. It's not hard to do with register handling, and often even saves you some logic.
2 replies
It's not required, tho, just ... something different I do
Taichi Ishitani
@taichi-ishitani
image.png
2 replies
Dan Gisselquist
@ZipCPU
Here's a blog article discussing that design, in case your are interested in how I handle register access: https://zipcpu.com/blog/2020/03/08/easyaxil.html
Doesn't look like I can see images from here.
Ahh ... found the link. Okay, I see it. Thanks!
Looking at it now.
What doesn't make sense is the other half of the sentence.
An AXI4 lite slave CANNOT be connected to a full AXI interface without modification. You'll always need to handle the AxLEN signals from AXI(full) when generating the slave signals, and then you'll need to work out RLAST and BVALID from the results.
1 reply
It's not trivial, but it is doable. (See, for example, https://github.com/ZipCPU/wb2axip/blob/master/rtl/axi2axilite.v )
Dan Gisselquist
@ZipCPU
The spec, IHI0022G is the version I have, discusses returning an error if you ever try to access an AXI4lite slave inappropriately. This isn't as easy as it sounds. For example, you cannot return an error if the error would come back out of order from something already going on internal to the slave.
At any rate, it's late here. I'll be back again on Monday.
stffrdhrn: Thanks for introducing @Harshitha172000. I look forward to interacting with her over the summer.
... and you know, I never inspected the APB bridge. That'd be a fun one to formally verify as well. ;)
Dan Gisselquist
@ZipCPU
In case you are interested, here's my own AXI-lite to APB bridge logic. You might note that I set the APB registers on a clock--not knowing how fast (or slow) the APB slave might be. It's a slighly different implementation, but one you might wish to look over. It's certainly simple enough.
ZipCPU @ZipCPU heads to bed ... really this time.
Taichi Ishitani
@taichi-ishitani
image.png