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Dan Gisselquist
@ZipCPU
Here's a blog article discussing that design, in case your are interested in how I handle register access: https://zipcpu.com/blog/2020/03/08/easyaxil.html
Doesn't look like I can see images from here.
Ahh ... found the link. Okay, I see it. Thanks!
Looking at it now.
What doesn't make sense is the other half of the sentence.
An AXI4 lite slave CANNOT be connected to a full AXI interface without modification. You'll always need to handle the AxLEN signals from AXI(full) when generating the slave signals, and then you'll need to work out RLAST and BVALID from the results.
1 reply
It's not trivial, but it is doable. (See, for example, https://github.com/ZipCPU/wb2axip/blob/master/rtl/axi2axilite.v )
Dan Gisselquist
@ZipCPU
The spec, IHI0022G is the version I have, discusses returning an error if you ever try to access an AXI4lite slave inappropriately. This isn't as easy as it sounds. For example, you cannot return an error if the error would come back out of order from something already going on internal to the slave.
At any rate, it's late here. I'll be back again on Monday.
stffrdhrn: Thanks for introducing @Harshitha172000. I look forward to interacting with her over the summer.
... and you know, I never inspected the APB bridge. That'd be a fun one to formally verify as well. ;)
Dan Gisselquist
@ZipCPU
In case you are interested, here's my own AXI-lite to APB bridge logic. You might note that I set the APB registers on a clock--not knowing how fast (or slow) the APB slave might be. It's a slighly different implementation, but one you might wish to look over. It's certainly simple enough.
ZipCPU @ZipCPU heads to bed ... really this time.
Taichi Ishitani
@taichi-ishitani
image.png

discusses returning an error

You say about this sentence?

Dan Gisselquist
@ZipCPU
taichi-ishitani: To test your logic, should I connect an rggen_apb_bridge to the rggen_axi4lite_adapter?
That'd at least produce a known protocol.
Taichi Ishitani
@taichi-ishitani
Hi @ZipCPU ,
You'd like to test generated RTL?
if yes, you can get generated RTL with AXI4 Lite IF from here.
https://github.com/rggen/rggen-sample-testbench/tree/master/rtl/axi4lite
Dan Gisselquist
@ZipCPU
taichi-ishitani: I don't get it. Why so much indirection? rggen_default_register is just a wrapper for rggen_register_common? Why have rggen_default_register at all then?
Taichi Ishitani
@taichi-ishitani

rggen_default_register

https://github.com/rggen/rggen-sv-rtl/blob/master/rggen_indirect_register.sv
rggen_indirect_register has also an instance of rggen_register_common. Therefore, I've introduced rggen_default_register to align hierarchy depth of rggen_register_common with an instance of rggen_register_common within rggen_indirect_register.

Aligning hierarchy depth is to simplify RAL model implementation.
rggen_register_common has an instance of helper module for simulation. RAL model can execute back door access via this helper module.
Taichi Ishitani
@taichi-ishitani
We need to use HDL path to the helper module to get handle of the helper module. To resolve HDL path easily, I've introduce rggen_default_register to align rggen_indirect_register.
https://github.com/rggen/rggen-sv-ral/blob/3b78350121430bf434e4a7cdc054a6d93f74e3c2/rggen_ral_backdoor_pkg.sv#L123
hdl_path[0].slices[0].path shows path to an instance of rggen_default_register or rggen_indirect_register.
u_register_common.u_backdoor shows path to the helper module.
Dan Gisselquist
@ZipCPU
taichi-ishitani: Well, okay. Let me ask this, though: Does your design, as posted, pass all of your tests? Are you aware of any deficiencies in it?
These are basic tests so some bit field types may not be tested enough.
Dan Gisselquist
@ZipCPU
taichi-ishitani: Okay, so ... here's why I'm interested: I've taken an interest in formally verifying AXI and AXI-lite components. When I find an open source component, I like to formally verify it to see if I can find any faults with it.
So, I pulled your design into SymbiYosys to see if I might find some faults.
However, my own perspective is quite biased. I tend to have an unfailing belief in formal methods, and also a strong prejudice against simulation based methods. This is based on my own experience which (sadly) is much too limited.
So ... I figured I'd ask you to see your thoughts on whether or not you felt your design was working, before revealing any of the bugs I've found using formal methods.
:D
Taichi Ishitani
@taichi-ishitani
I've tested my axi4 lite bridge with simple sequence only and have not yet tested it with stressful access sequences.
Therefore, I'm not sure whether or not the bridge module always works well.
Dan Gisselquist
@ZipCPU
That's fair enough.
Have you tried using SymbiYosys at all?
Taichi Ishitani
@taichi-ishitani
so your trial by using formal methods increases quality of my axi4 lite bridge module :)

Have you tried using SymbiYosys at all?

no I have not yet. What kind of tool?

Dan Gisselquist
@ZipCPU
SymbiYosys uses Yosys to convert a Verilog design into a formal property description, suitable for a formal solver to work with.
If you add your design to a set of AXI-lite properties, such as those found here: https://github.com/ZipCPU/wb2axip/blob/master/bench/formal/faxil_slave.v
You can then check whether or not your design meets the criteria for being a valid AXI4-lite slave.
I use SymbiYosys quite regularly with just about all of my designs, and certainly with any design that will ever touch a bus of any type.
It gives me a strong confidence that my designs work.
Taichi Ishitani
@taichi-ishitani
To verify converted formal properties, we need to use formal verification tool (VC formal, jasper)?
Dan Gisselquist
@ZipCPU
No. Yices works just fine, as does Boolector.
I'm using yices so far for my tests. Everything I've done at this point has all been open source.
Taichi Ishitani
@taichi-ishitani
Thanks for the information. Sounds good!
Dan Gisselquist
@ZipCPU
taichi-ishitani: Here are two traces, showing how well your design works (when it works): https://imgur.com/a/09SG0je