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Dan Gisselquist
@ZipCPU
Have you tried using SymbiYosys at all?
Taichi Ishitani
@taichi-ishitani
so your trial by using formal methods increases quality of my axi4 lite bridge module :)

Have you tried using SymbiYosys at all?

no I have not yet. What kind of tool?

Dan Gisselquist
@ZipCPU
SymbiYosys uses Yosys to convert a Verilog design into a formal property description, suitable for a formal solver to work with.
If you add your design to a set of AXI-lite properties, such as those found here: https://github.com/ZipCPU/wb2axip/blob/master/bench/formal/faxil_slave.v
You can then check whether or not your design meets the criteria for being a valid AXI4-lite slave.
I use SymbiYosys quite regularly with just about all of my designs, and certainly with any design that will ever touch a bus of any type.
It gives me a strong confidence that my designs work.
Taichi Ishitani
@taichi-ishitani
To verify converted formal properties, we need to use formal verification tool (VC formal, jasper)?
Dan Gisselquist
@ZipCPU
No. Yices works just fine, as does Boolector.
I'm using yices so far for my tests. Everything I've done at this point has all been open source.
Taichi Ishitani
@taichi-ishitani
Thanks for the information. Sounds good!
Dan Gisselquist
@ZipCPU
taichi-ishitani: Here are two traces, showing how well your design works (when it works): https://imgur.com/a/09SG0je
That said, this is ... one of the most complex AXI-lite designs I've examined so far. It seems kind of strange, though, for a protocol which is (supposed to be) a lite version of AXI, or for that matter something that should be as simple as a basic register controller.
Taichi Ishitani
@taichi-ishitani

one of the most complex AXI-lite designs I've examined so far.

This module has a state machine to control request ready and response valid so you think so.
Generated modules may be connected with other modules cascadingly and so, in some case, it will take multiple cycles to get read data.
Therefore, I've implement the bridge module that way.

Dan Gisselquist
@ZipCPU
Here are the files I used when running SymbiYosys: https://gist.github.com/ZipCPU/05c2182cd833a243709db537b7953821
You'll still need the AXI-lite slave property set, but after that you should have everything you need to repeat my experiments with your design.
The AXI-slave property set is posted, just not in the same place. You can find that here: https://github.com/ZipCPU/wb2axip/blob/master/bench/formal/faxil_slave.v
Taichi Ishitani
@taichi-ishitani
connect my generated module and your formal AXI driver then I can verify my design by using SymbiYosys tool. Correct?
Dan Gisselquist
@ZipCPU
The design I just shared on gist.github.com does exactly that
Taichi Ishitani
@taichi-ishitani
Thanks. I understand. I will try to use SymbYosis tool.
Dan Gisselquist
@ZipCPU
taichi-ishitani: Still haven't tried formal methods?
Dan Gisselquist
@ZipCPU
taichi-ishitani: Here's a trace SymbiYosys is giving me. https://imgur.com/CAyxr3h This would crash Xilinx's (new) AXI Smartconnect interconnect.
Taichi Ishitani
@taichi-ishitani
I have not yet tried. New project for work is just started so I'm very busy.
Dan Gisselquist
@ZipCPU
Ok
Taichi Ishitani
@taichi-ishitani

https://github.com/rggen/rggen-verilog-rtl/blob/700657593c90e34db4f02f2ffc26664bb8939749/rggen_axi4lite_adapter.v#L215
This is handshake logic for write/read response.

  • w_bus_valid will be asserted when r_response_valid eq 0
  • r_response_valid will be de-asserted when response handshake is completed

Therefore, waveform which you show is strange.

Dan Gisselquist
@ZipCPU
taichi-ishitani: Okay, found the issue. I had the core configured for a synchronous reset.
Dan Gisselquist
@ZipCPU
:/
My apologies.
Taichi Ishitani
@taichi-ishitani
No problem :)
tgingold
@tgingold
3/ is the way to go. The needed information is already extracted. I will to do it.
I am not sure what do you mean by 'translate aggregates'. But yes, it is chain of choices.
Olof Kindgren
@olofk
Don't miss the next edition of FOSSi Dial-Up tomorrow https://www.fossi-foundation.org/dial-up/
hkalbasi
@hkalbasi:mozilla.org
[m]
Hi, why rocket chip and boom isn't on the librecore directory of cores?
Dan Gisselquist
@ZipCPU
The librecore registry of cores is (generally) generated by the core authors.
hkalbasi
@hkalbasi:mozilla.org
[m]
So can someone add them or it is against the rules of librecore?
Dan Gisselquist
@ZipCPU
Don't know. Let's see if someone else here does.
Jonathan Balkind
@Jbalkind
projects are listed under a username, not just the project name
so it might be a little strange for it to be randomperson/rocket or randomperson/boom
but I don't recall if there was any structural limitation against doing so
Olof Kindgren
@olofk
That's correct. It would be preferred if e.g. chipsalliance added rocket and whoever is in charge of boom adds it, but it's technically fine to add someone else's project. If the author wants to have it under their namespace we can probably move it later worst case
Stafford Horne
@stffrdhrn

We could raise issues on the github projects to request adding to Librecores.

https://github.com/riscv-boom/riscv-boom/issues
https://github.com/chipsalliance/rocket-chip/issues

Olof Kindgren
@olofk
@stffrdhrn Yes! That's a great idea
Taichi Ishitani
@taichi-ishitani
Hi all,
RgGen supports the "plugin" feature to customize RgGen to your environment.
I posted an article about this "plugin" feature to Linkedin.
Please see the following link:
https://www.linkedin.com/posts/taichi-ishitani-28237370_rggenrggen-activity-6819269551671394304-HS4c
Dan Gisselquist
@ZipCPU
taichi-ishitani: o/