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  • Aug 11 02:24
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Dan Gisselquist
@ZipCPU
taichi-ishitani: Here are two traces, showing how well your design works (when it works): https://imgur.com/a/09SG0je
That said, this is ... one of the most complex AXI-lite designs I've examined so far. It seems kind of strange, though, for a protocol which is (supposed to be) a lite version of AXI, or for that matter something that should be as simple as a basic register controller.
Taichi Ishitani
@taichi-ishitani

one of the most complex AXI-lite designs I've examined so far.

This module has a state machine to control request ready and response valid so you think so.
Generated modules may be connected with other modules cascadingly and so, in some case, it will take multiple cycles to get read data.
Therefore, I've implement the bridge module that way.

Dan Gisselquist
@ZipCPU
Here are the files I used when running SymbiYosys: https://gist.github.com/ZipCPU/05c2182cd833a243709db537b7953821
You'll still need the AXI-lite slave property set, but after that you should have everything you need to repeat my experiments with your design.
The AXI-slave property set is posted, just not in the same place. You can find that here: https://github.com/ZipCPU/wb2axip/blob/master/bench/formal/faxil_slave.v
Taichi Ishitani
@taichi-ishitani
connect my generated module and your formal AXI driver then I can verify my design by using SymbiYosys tool. Correct?
Dan Gisselquist
@ZipCPU
The design I just shared on gist.github.com does exactly that
Taichi Ishitani
@taichi-ishitani
Thanks. I understand. I will try to use SymbYosis tool.
Dan Gisselquist
@ZipCPU
taichi-ishitani: Still haven't tried formal methods?
Dan Gisselquist
@ZipCPU
taichi-ishitani: Here's a trace SymbiYosys is giving me. https://imgur.com/CAyxr3h This would crash Xilinx's (new) AXI Smartconnect interconnect.
Taichi Ishitani
@taichi-ishitani
I have not yet tried. New project for work is just started so I'm very busy.
Dan Gisselquist
@ZipCPU
Ok
Taichi Ishitani
@taichi-ishitani

https://github.com/rggen/rggen-verilog-rtl/blob/700657593c90e34db4f02f2ffc26664bb8939749/rggen_axi4lite_adapter.v#L215
This is handshake logic for write/read response.

  • w_bus_valid will be asserted when r_response_valid eq 0
  • r_response_valid will be de-asserted when response handshake is completed

Therefore, waveform which you show is strange.

Dan Gisselquist
@ZipCPU
taichi-ishitani: Okay, found the issue. I had the core configured for a synchronous reset.
Dan Gisselquist
@ZipCPU
:/
My apologies.
Taichi Ishitani
@taichi-ishitani
No problem :)
tgingold
@tgingold
3/ is the way to go. The needed information is already extracted. I will to do it.
I am not sure what do you mean by 'translate aggregates'. But yes, it is chain of choices.
Olof Kindgren
@olofk
Don't miss the next edition of FOSSi Dial-Up tomorrow https://www.fossi-foundation.org/dial-up/
hkalbasi
@hkalbasi:mozilla.org
[m]
Hi, why rocket chip and boom isn't on the librecore directory of cores?
Dan Gisselquist
@ZipCPU
The librecore registry of cores is (generally) generated by the core authors.
hkalbasi
@hkalbasi:mozilla.org
[m]
So can someone add them or it is against the rules of librecore?
Dan Gisselquist
@ZipCPU
Don't know. Let's see if someone else here does.
Jonathan Balkind
@Jbalkind
projects are listed under a username, not just the project name
so it might be a little strange for it to be randomperson/rocket or randomperson/boom
but I don't recall if there was any structural limitation against doing so
Olof Kindgren
@olofk
That's correct. It would be preferred if e.g. chipsalliance added rocket and whoever is in charge of boom adds it, but it's technically fine to add someone else's project. If the author wants to have it under their namespace we can probably move it later worst case
Stafford Horne
@stffrdhrn

We could raise issues on the github projects to request adding to Librecores.

https://github.com/riscv-boom/riscv-boom/issues
https://github.com/chipsalliance/rocket-chip/issues

Olof Kindgren
@olofk
@stffrdhrn Yes! That's a great idea
Taichi Ishitani
@taichi-ishitani
Hi all,
RgGen supports the "plugin" feature to customize RgGen to your environment.
I posted an article about this "plugin" feature to Linkedin.
Please see the following link:
https://www.linkedin.com/posts/taichi-ishitani-28237370_rggenrggen-activity-6819269551671394304-HS4c
Dan Gisselquist
@ZipCPU
taichi-ishitani: o/
Rafael Pereira
@rnp:matrix.org
[m]

it is kind of off-topic, but worth to mention, in case it is not yet known:

Use Sigasi Studio with your Open Source projects
https://www.sigasi.com/news/open-source-program/

Dan Gisselquist
@ZipCPU
Hmm ... they must be struggling to sell licenses ...
Husni Faiz
@drac98_gitlab

Hi all, I sent an email to discussion@lists.librecores.org but there wasn't any response. Is the mailing list still active?
I'm copying the same message here.

I'm a 3rd year undergraduate student who has started to explore FPGAs and RISC-V.

I saw the project "RISC-V core with AI Acceleration synthesizable with open source tools" under the GSoC 2021 projects. If this project is still open, I would like to try this for my semester project which is about 3-4 months long. I'll be able to put in about 8hrs/week for the project.

Would this be an achievable milestone within the timeline? If not, what changes can I make for the project to fit the timeline?

I have a BASYS 3 board (Artix-7 FPGA). Would that work for this project?

Olof Kindgren
@olofk
Hi @drac98_gitlab . Google Summer of Code is over for this year. You can find more info about GSoC here https://summerofcode.withgoogle.com/
Jonathan Balkind
@Jbalkind
also @drac98_gitlab there was a response so perhaps it's in your spam
because it went into my spam too
Olof Kindgren
@olofk
Interesting. I incidentally just found the reply in my spam too five minutes ago
Husni Faiz
@drac98_gitlab

Hi @olofk @Jbalkind . Thank you for the responses. I found the email in the spam. that's odd. I should add a filter for the mail.

I actually I participated in GSoC 2021 in the RTEMS Project .
I came across FOSSi while looking for GSoC 2021 project and I found the AI Acceleration project. At that time I wasn't confident enough to do it as a GSoC project. But I really want to try it out and contribute. So I thought to do it as my current semester project. I'm a total beginner. Please help me out.

Jonathan Balkind
@Jbalkind
the mentors' email addresses are listed on the GSoC projects page, you should try getting in touch with them
Husni Faiz
@drac98_gitlab
Okay :thumbsup:
Husni Faiz
@drac98_gitlab
Hi @jeremybennett. I sent an email to you. I hope it doesn't go to the spam ;)
rnp
@rnp:matrix.org
[m]
Is there an opensource unit testing framework for SystemVerilog, featurewise like VUnit for VHDL? The use case is to use it on existing SystemVerilog testbenches (I am aware of cocotb, but if I understood correctly, in this case one has to re-write the testbenches in Python).
Colin Marquardt
@cmarqu
There is http://agilesoc.com/open-source-projects/svunit/, but I'm not sure about how it compares to VUnit. OTOH, VUnit is not exclusively for VHDL, it's just more mature in that area.
1 reply
Unai Martinez-Corral
@umarcor

Actually, there is interest in hopefully combining VUnit and SVUnit in the future. See https://umarcor.github.io/osvb/intro/index.html:

While VUnit provides multiple optional helper VHDL libraries, the SystemVerilog infrastructure is limited to the HDL runner and some check features. Conversely, SVUnit is for SystemVerilog mostly. The test management features in SVUnit are implemented using Perl, and installation scripts are written in bash/csh. As a result, it would be interesting to handle SVUnit’s HDL resources through VUnit’s simulator interface and runner. There is no work in progress in this regard yet.

Maintainers of VUnit and SVUnit did talk about it, but it's not a priority for any of them.
On the other hand, VUnit was not tested with open source (System) Verilog simulators (iverilog, verilator) for some years now. Nowadays, those might work, which would make it easier for the community to try integrating the SV utilities from SVUnit.