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  • Oct 18 15:39
    rswarbrick edited #277
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  • Oct 06 22:25
    imphil commented #275
Olof Kindgren
@olofk
It looked fine in the Vivado schematic GUI at least
I think the EDIF is fine
The code is not super complicated https://github.com/fusesoc/blinky/blob/master/blinky.v
I'll try to hard code clk_freq_hz and see if there's some issues with the parameters
Karol Gugala
@kgugala
maybe constraints are not passed correctly
Olof Kindgren
@olofk
Timing constraints?
Karol Gugala
@kgugala
the whole xdc file(s)
Olof Kindgren
@olofk
I think that should be ok. Vivado seems to at least pick up the pinout correctly and the timing reports look sensible
Will try to simplify the code even further to make it easier to see where it goes wrong
Olof Kindgren
@olofk
Very strange. Maybe I need to reverse engineer the netlist at this point and see what the hell it's implementing
Karol Gugala
@kgugala
you can check for wierd optimization messages in Vivado log
like - "it seems the whole design does nothing, so I'll remove it" ;)
Olof Kindgren
@olofk
I get nothing. Not a single warning and the implemented netlist loks fine
If it had at least optimized away everything I would have something to look for :)
Trying a different yosys in case my native one is too old
I really like how easy it is nowadays to use different tools with Edalize :)
Karol Gugala
@kgugala
there should be some kind of award for easiness ;)
Olof Kindgren
@olofk
Nope. No change :(
I agree :)
hmm... now I got something strange. It can't generate a schematic because count[0] is not connected to anything. Wonder if there's some connectivity issue in the netlist
Olof Kindgren
@olofk
Or maybe that's something else
ehmm....
Olof Kindgren
@olofk
ok, so the code now has a 5-bit counter and an extra ff on the output. When Vivado's placer is done, there are only two FFs left
Olof Kindgren
@olofk
Hmmm.. it does look like there are some connectivity issues in the edif. I should probably visualize what yosys sees before writing the edif
And what the json netlist looks like in netlistsvg
I give up
Karol Gugala
@kgugala
I'll try to do some tests in the evening
Olof Kindgren
@olofk
This is what I ended up with
module blinky
  #(parameter clk_freq_hz = 0)
   (input  clk,
    output reg q = 1'b0);

   reg [4:0] count = 0;

   always @(posedge clk) begin
      q <= count[4];

      count <= count + 1;
   end

endmodule
Karol Gugala
@kgugala
and the latest edalize?
Olof Kindgren
@olofk
Yes
oh... should try an older edalize in case I messed up something
Nope, same
Olof Kindgren
@olofk
@kgugala Ok, so apparently I'm not very good at giving up. Did some more tests today and got it working! The issue was a missing -pvector bra in the edif options. I remember seeing that somewhere but it must have gotten lost at some point. Weird that I didn't catch it in the tests. Is this exclusively for use with Vivado, or should it be set for other tools too?
Ahh.. it's passed to the template, but the template never picks it up.
Probably broken since the custom yosys template feature then :/
It would be much easier to maintain Edalize if people didn't write all these EDA tools :)
Karol Gugala
@kgugala
could be, great you found it
I wasn't able to check this - I got my second covid shot yesterday and since then my new 5G nanochips are updating giving me some fever ;)
Olof Kindgren
@olofk
Oh no! You are one of them now. Didn't you know that the pandemic is just a hoax so that the government can have an opportunity to change batteries in all the birds? ;)
Karol Gugala
@kgugala
cannot talk now, switching my Linux installation to Windows ;)
Olof Kindgren
@olofk
удачи!
Olof Kindgren
@olofk
Hey @zarubaf, you here? Got a Morty question
Carlos Alberto Ruiz Naranjo
@qarlosalberto
hey guys! Is it necessary the MODEL_TECH environment variable to simulate with ModelSim? I have ModelSim in the system path
is there any documentation about the variables needed for each simulator?
Olof Kindgren
@olofk
@qarlosalberto Yes. $MODEL_TECH is required. It's a questionable design decision though :) IIRC, the only time it's really needed is for building VPI stuff because you need to include directories relative to $MODEL_TECH. We could probably figure out the correct include dir if we know where the vsim binary is, so having it in path should be enough really
No list of required env vars either. The only one I can see from a quick look is INTERCHANGE_SCHEMA_PATH, when symbiflow is used with the interchange_fpga arch
Carlos Alberto Ruiz Naranjo
@qarlosalberto
okok!
synth, hw_target...
but I haven't seen that options in the documentation