Where communities thrive


  • Join over 1.5M+ people
  • Join over 100K+ communities
  • Free without limits
  • Create your own community
People
Activity
  • Aug 12 00:04
    hossein1387 closed #499
  • Aug 12 00:04
    hossein1387 commented #499
  • Aug 10 08:59

    olofk on master

    Add CLI for listing tool backen… (compare)

  • Aug 10 08:59
    olofk closed #583
  • Aug 08 16:41
    joennlae closed #582
  • Aug 08 16:41
    joennlae commented #582
  • Aug 08 15:12
    skilambi commented #584
  • Aug 08 14:35
    shareefj commented #584
  • Aug 08 14:03
    skilambi commented #584
  • Aug 08 13:55
    shareefj commented #584
  • Aug 08 13:06
    skilambi opened #584
  • Aug 07 08:19
    olofk synchronize #583
  • Aug 07 08:19

    olofk on list_tools

    Add CLI for listing tool backen… (compare)

  • Aug 07 08:16
    olofk commented #583
  • Aug 06 19:18
    gojimmypi opened #15
  • Aug 05 21:54
    olofk opened #583
  • Aug 05 21:50

    olofk on list_tools

    Add CLI for listing tool backen… (compare)

  • Aug 03 15:10
    imphil commented #582
  • Aug 03 12:30
    olofk closed #580
  • Aug 03 12:29
    olofk commented #580
trayres
@trayres
Like can it provide parameters if the top level is a config statement
Tim 'mithro' Ansell
@mithro
@matthewvenn - Just published a walkthrough video showing all the steps needed to get a design ready for submission to the 6th SkyWater Google Shuttle! - https://www.youtube.com/watch?v=MNuoYz_MM-c
fantognazza
@fantognazza:matrix.org
[m]
Hello, after reading the FuseSoC documentation, I couldn't find a way to expose a parameter of a generator configuration up to the command line argument.
Am I wrong?
Going more into detail, I wrote a generator to create a time constraint file for Vivado given a frequency in input.
I would like to propagate the parameter from the command line argument rather than hard-coding all possible frequencies that a design could target.
This approach would enable the creation of some automation tasks, such as a bisection algorithm to determine the maximum frequency achievable by a synthesized design
3 replies
m-kru
@m-kru
@olofk Why is actually the term "logical_name" used for library name?
1 reply
Euripedes
@euripedesrocha
Hi, any documentation on adding a new backend to edalize? I started to add a GowinEDA backend and tried it from fusesoc and it wasn't found(For now I just created .py files from vivado backend)
Arman Avetisyan
@armleo

Does anybody know how to actually run the fusesoc with yosys? I don't think there is proper documentation answering my question. I created my own .core with my file lists, and I don't know if I am supposed to do something else too?

I get following error.

fusesoc run
usage: fusesoc run [-h] [--no-export] [--build-root BUILD_ROOT] [--setup]
[--build] [--run] [--target TARGET] [--tool TOOL]
[--flag FLAG] [--system-name SYSTEM_NAME]
system ...
fusesoc run: error: the following arguments are required: system, backendargs

Arman Avetisyan
@armleo
[armleo@armleo-virtualbox armleo_burstmem]$ fusesoc core show armleo:armleo_cores:armleo_burstmem
ERROR: 'armleo:armleo_cores:armleo_burstmem' or any of its dependencies requires 'armleo_burstmem', but this core was not found
Arman Avetisyan
@armleo

Okay, I solved it.

fusesoc --cores-root . run --target=synth --tool=yosys armleo:armleo_cores:armleo_burstmem

  1. The cores root need to be specified before run command.
5 replies
Julien de Castelnau
@panther03
quick question, does fusesoc support having multiple testbenches? looks like you could hack it with yaml anchors and adding a target for each testbench but i'm curious if there's a cleaner way to do it
cause then you'd have to call fusesoc for each target, whereas it'd be nice to run the entire suite of testbenches with one command
2 replies
Julien de Castelnau
@panther03
Also, what's the best way to disable certain steps in the run process? More specifically, I'm trying to run my IP cores through synthesis to ensure they meet timing, have no latches, and fit in the FPGA, but I'm not interested generating a bitstream or trying to program the FPGA, because it's just a piece of a larger design. Is there a standard/clean way of doing this?
7 replies
trayres
@trayres
Hey everyone - can I have a git provider in FuseSoc call a certain TAG?
1 reply
Like master branch, tag XYZ?
Or just TAG XYZ, I guess
I'm pretty sure there is, but I was hoping somebody had an example handy. If I find out before somebody answers I'll post it here in case someone else is looking :)
Julien de Castelnau
@panther03
How is the reporting module in edalize meant to be used right now? I don't see any code paths in fusesoc that invoke it. I'm not sure if I have the right package feature installed or if it's just not implemented?
1 reply
Saaswath
@infini8-13
Hey, how I can I make a core available thru fusesoc? It'll helpful if anyone can give a bit of guidance for this. Thanks!
3 replies
Dan Petrisko
@dpetrisko
Hi, is there a way in fusesoc to use external filelists for your core file? I have some IP which contains flists in VCS/Verilator/most simulators format, and would like to reuse without rewriting
1 reply
trayres
@trayres
Hey everybody - I think I ran into an issue. If I have multiple tags for a repository, it looks like FuseSoC isn't grabbing all the tags because FuseSoC is doing a shallow clone (--depth 1)?
16 replies
Tiny Labs
@tinylabs
Hello all. I'm working on a project using spartan6 and hoping to use a yosys->ise pnr flow. Does anyone know of an example project like this? I'm coming up empty on my searches. Thanks!
Tiny Labs
@tinylabs
It seems to complain about yosys_as_subtool:
'''
targets:
pano_g2:
default_tool: yosys
filesets: [rtl, scripts, constraints]
toplevel: [top]
tools:
yosys:
arch: xilinx
output_format: edif
yosys_as_subtool: True
ise:
family: spartan6
device: xc6slx100
package: fgg484
speed: -2
'''
Without that it generates the edif fine but doesn't invoke ise for place and route
Olof Kindgren
@olofk

@tinylabs yosys_as_subtool is an internal parameter that shouldn't be set by the user (it really shouldn't be exposed at all, but we haven't fixed that).

You should instead use ise as the default_tooland then set synth : yosys, BUT! It turns out that using yosys as a frontend for ISE isn't implemented. I could swear I had implemented that but can't find any trace of it now

Tiny Labs
@tinylabs
Thanks @olofk! I could've sworn I've seen an example with this flow as some point but I must be misremembering. There's a small but dedicated community around these panologic devices from a now defunct company. They use the largest spartan6 parts so everyone is stuck using ISE. Most of my IP is in systemverilog so now that yosys supports the surelog flow I plan on setting up a proper toolchain using yosys->ise.
Keep an eye out for a PR. It won't be as complete as the Vivado refactoring but it will allow the stuck ISE users a means to synthesize system verilog
Olof Kindgren
@olofk
@tinylabs Will happily accept such a patch. I have similar use cases where the devices are only supported by ISE, but the ISE verilog parser is just so old it's getting harder to make it accept modern code
Tiny Labs
@tinylabs
@olofk - Currently working on an edalize patch but it's not finding my new ise templates. Maybe my dev environment isn't correct? Backtrace here: https://pastebin.com/raw/bxjrtCc7
Templates are in the directory:
(env) elliot@pop-os:~/projects/edalize$ ls -l edalize/templates/ise/
total 4
-rw-rw-r-- 1 elliot elliot 0 Jun 18 13:17 ise-program.tcl.j2
-rw-rw-r-- 1 elliot elliot 1519 Jun 18 13:15 ise-project.tcl.j2
-rw-rw-r-- 1 elliot elliot 0 Jun 18 13:17 ise-run.tcl.j2
-rw-rw-r-- 1 elliot elliot 0 Jun 18 13:17 ise-synth.tcl.j2
and I setup edalize using 'pip install -e .' from the forked edalize root
Tiny Labs
@tinylabs
@olofk - Ignore, I figured it out
Tiny Labs
@tinylabs
@olofk - I have a working yosys->ise flow in this fork: https://github.com/tinylabs/edalize.git. The problem I'm hitting is when adding an additional tclSource file containing ISE statements it also gets pulled into yosys. Now vivado has alternate file types for tcl (XDC/SDC) so it's not a problem. I ended up adding a new file type iseTclSource but I'm not sure that's the best solution.
Stefan
@Steinegger
I ran into some troubles with the xsim backend and blockdesigns. For the vivado backend I'm exporting the blockdesign as a tcl script and run that with a tcl script that also makes vivado generate the wrapperfile. However, I can't seem to get it to work with xsim and the edalize backend seems to only support a smaller fraction of file-types. Is there a way to do this?
Tim 'mithro' Ansell
@mithro
People here might find https://github.com/Blokkendoos/AACircuit entertaining! -- Draw electronic circuits with ASCII characters.
1 reply
Adithya Sunil
@adithyasunil26
Hi, I am working on a fusesoc core for blackparrot and while running the verilator lint target I am running into import errors because of package files being placed in the wrong order in the .vc generated. Is there a way for me to put certain files on top in the .vc from the fusesoc core? Or are there any other fixes to this issue?
Thanks!
Dan Petrisko
@dpetrisko
More context for Adithya’s issue: verilator/verilator#2890. This appears to be a Verilator-specific problem, other tools happily accept OOO flists if imports and includes are properly followed
Zeeshan Rafique
@zeeshanrafique23
Hi @adithyasunil26
I have seen few implementations where people put sv packages into a separate core file and include those files only where they are needed.
You can check lowRISC/ibex for reference.
Adithya Sunil
@adithyasunil26
Hi @zeeshanrafique23
Ooo that does sound like a good solution. Will give it a shot.
Thanks!
m-kru
@m-kru
Does anyone have any example .core file for running a simulation in Vivado?
2 replies
Ok, there is xsim backend.
Hossein Askari
@hossein1387
what is the best way to pass parameters to gui mode? I am working with Vivado and most of the time batch mode (just terminal output) is fine. But when I need to look into waveforms, I have to manually put the parameters from the simulation target into the Makefile that fusesoc generates. Here is my core file: https://github.com/hossein1387/BARVINN/blob/APB/barvinn.core. I need to pass firmware and rodata parameters to Vivado.
I would appreciate it if someone could help me with this.
gojimmypi
@gojimmypi
Greetings. I've recently added a PR to SERV and fusesoc repos for ICE-V Wireless support! My first ever SERV core was on a board not previously supported! Woohoo!! (Ok, its really just another iCE40, so I just leveraged the iCEBreaker examples and added the appropriate pcf).
Stefan
@Steinegger
I noticed that fusesoc/edalize automatically upgrade xci files in the vivado project template. Isn’t that kinda a bad idea for any reproducibility?
4 replies
Stefan
@Steinegger
If you have an xci file that specifies e.g. version 1.5, but you ip catalogue has 1.9 this line ensures that 1.9 is going to be used:
https://github.com/olofk/edalize/blob/8c97cb9d72afc438d8d827421a7355f58178968c/edalize/tools/templates/vivado/vivado-project.tcl.j2#L76
2 replies
Which is fine for many cases but breaks everything if there’s API changes in cores that one might want to deal with only at a later point
migellito
@migellito

Hello @olofk
Could you please clarify
I've tried to pass parameters to generator inline:

generate:                                                                                                        
  - generated_top : {tech : asic}

and it worked fine
Then I've tried to use --flag option:
fusesoc run --target syn --flag=tech_asic my:project:top
it is working OK in generate section:

generate:                                                                                                        
  - tech_asic? (generated_top_asic)

But if I try to use combination of this:

generate:                                                                                                        
  - tech_asic? (generated_top : {tech : asic})

It throws error:

yaml.parser.ParserError: while parsing a block mapping
 in "top.core", line 76, column 9
did not find expected key
 in "top.core", line 76, column 56

Is it me doing something wrong or does this function is NYI ?

Tiny Labs
@tinylabs
Hello all. I'm using the following branch for yosys https://github.com/antmicro/yosys-uhdm-plugin-integration.git with uhdm integration. I'm looking to load the systemverilog plugin. I can see there is a macro in tools/templates/yosys/edalize_yosys_procs.tcl.j2 to load_plugins but I can't figure out how to set the variable. Has anyone done this?
Tiny Labs
@tinylabs
Alternatively, if anyone knows of a project generates a uhdm file using surelog that would work too