librecores/gsoc-museum-edsac

Hatim Kanchwala

@hatimak

@jeremybennett will do that 👍

for the day of orconf pres, i was thinking of choosing 9th and 10th. allowing 8th as a buffer between chiphack pres and orconf. @maryEmbecosm and i could probably tune our pres’ during buffer

Jeremy Bennett

@jeremybennett

@hatimak That sounds reasonable. I suggest you indicate preferred days. I see the paper submission form has a section to specify days you can talk. I also see that although you can only specify one email address, you can specify the names of multiple authors.

Hatim Kanchwala

@hatimak

good morning

@jeremybennett and @wallento, i would like to share updates regarding my application to university for funds. i have already prepared all the necessary letters and expense estimates and sent it to the dean's office along with your letters

but i am being made to spend a fair amount of unfruitful time doing these procedures

Hatim Kanchwala

@hatimak

my question is, to apply for a UK visa, i need to indicate how my trip is going to be financed, so what should i put in there? i don't have a confirmation letter from the university yet, but i am afraid that delaying visa application might put me in a tight situation

Jeremy Bennett

@jeremybennett

@hatimak I would put down that FOSSi and Embecosm are funding you, since we have agreed that even if your Dean does not supply funds, we will ensure you are covered. I think it is fruitful time, because it will look very good on your resume if as an undergraduate you have managed to secure Dean's funding.

@wallento Does this seem reasonable to you. We'll have to prepare a letter for the visa authorities confirming this. If you are happy, we can prepare that here, and I can ask Simon to sign as FOSSi secretary.

Hatim Kanchwala

@hatimak

@jeremybennett thank you for the advice :) i will move forward with the visa application the way you suggest

Stefan Wallentowitz

@wallento

yes, that makes sense, @jeremybennett

best way to get it signed apparently

Jeremy Bennett

@jeremybennett

I've asked Judith Jones to put the letter together for you.

Hatim Kanchwala

@hatimak

thank you very much @jeremybennett

Hatim Kanchwala

@hatimak

hello @jeremybennett @wallento. i am behind schedule this week. have been sick for past 2-3 days. got drenched in a heavy shower here and caught a severe cold. have a sore throat but i should be fine in a day or two. i am very sorry. please accept my apology.

Stefan Wallentowitz

@wallento

no problem. careful recovery should be your number one priority, I am sure you will catch up when fit again

Hatim Kanchwala

@hatimak

thank you @wallento :)

Jeremy Bennett

@jeremybennett

@hatimak No problem, get well soon. If you are well by Friday we can have our call, but otherwise we can postpone until Monday. I can do your stage 2 report (which will be fine) on the basis of all the work you have done so far.

@hatimak And don't worry about catching up your schedule. Part of project management is about recognizing when people get sick and adjusting plans - I'm sure there are things we can drop from your schedule, which won't materially affect your success.

Hatim Kanchwala

@hatimak

thank you @jeremybennett :) you are very kind. may i confirm by end of day today whether i can join the meeting on friday?

Hatim Kanchwala

@hatimak

https://hangouts.google.com/hangouts/_/calendar/azVlZ3JybTNuajg1cWZtYmE4dWs1bnU5aTRAZ3JvdXAuY2FsZW5kYXIuZ29vZ2xlLmNvbQ.mog4h6dbrqeejro3akbf2ngq40?authuser=0

Stefan Wallentowitz

@wallento

hi guys, sorry, I cannot make it

Dan Gorringe

@DanGorringe

Hi Hatim, Where can I find the verilog to upload to the myStorm board?

Hatim Kanchwala

@hatimak

hello dan

@DanGorringe ^

you can find most of the verilog in our repo

but if you run into issues please email me

i have classes/lab/tutorials from 9-6 IST almost every weekday

Hatim Kanchwala

@hatimak

mon, tue and fri are the busiest

Jeremy Bennett

@jeremybennett

@hatimak Have you thought about how you are going to make your final submission. I would have thought you could link to the repo, since it is solely for this GSoC project. But if you do this, you'll need to write a comprehensive README.md file.

Possibly supplemented by a blog post and reference to the Wiki.

Jeremy Bennett

@jeremybennett

@hatimak I hope you are recovering. I am on vacation this week, but available for a review today if you are well enough

Hatim Kanchwala

@hatimak

@jeremybennett, i am admitted in the hospital. on a multivitamin and antibiotic course. fever broke yesterday so doctor says it is sign of recovery

Jeremy Bennett

@jeremybennett

@hatimak Very sorry to hear you are in hospital, but glad you are recovering. Hope you get better soon.

Jeremy Bennett

@jeremybennett

@hatimak Have you recovered fully? If so we should have a hangout ASAP. I also understand from Ken Boak that you have a problem with your MyStorm board. Do we need to ship you a new one?

Jeremy Bennett

@jeremybennett

@here Hangout will be 10am UK time (11am Germany, 2:30pm India). Connect at https://plus.google.com/hangouts/_/calendar/azVlZ3JybTNuajg1cWZtYmE4dWs1bnU5aTRAZ3JvdXAuY2FsZW5kYXIuZ29vZ2xlLmNvbQ.mog4h6dbrqeejro3akbf2ngq40

Stefan Wallentowitz

@wallento

oh, sorry

I am sick in bed and missed it

Hatim Kanchwala

@hatimak

i just noticed that github shows our repository to have over 90% of AGS script. does anybody know why it does not show verilog instead?

https://pasteboard.co/GIji3lj.png

Jeremy Bennett

@jeremybennett

@hatimak Curious. Not sure how this happens - I

Jeremy Bennett

@jeremybennett

We think it might be the non Verilog files in the dev branch confusing git. You've committed the bitstreams. The master branch shows 100% Verilog.

You might like to remove the generated binaries (and put them in .gitignore).

If you do git diff --name-only github/master | grep -v '\.v', you get

doc/gating_emfs.md
src/edsac/Makefile
src/edsac/blackice.pcf
src/peripherals/lcd/Makefile
src/peripherals/lcd/blackice.pcf
test/mystorm/delay/Makefile
test/mystorm/delay/blackice.pcf
test/mystorm/delay/chip.asc
test/mystorm/delay/chip.bin
test/mystorm/delay/chip.blif
test/mystorm/delay_line/Makefile
test/mystorm/delay_line/blackice.pcf
test/mystorm/delay_line/chip.asc
test/mystorm/delay_line/chip.bin
test/mystorm/delay_line/chip.blif
test/mystorm/digit_pulse_generator/Makefile
test/mystorm/digit_pulse_generator/blackice.pcf
test/mystorm/digit_pulse_generator/chip.asc
test/mystorm/digit_pulse_generator/chip.bin
test/mystorm/digit_pulse_generator/chip.blif
test/mystorm/flipflop/Makefile
test/mystorm/flipflop/blackice.pcf
test/mystorm/flipflop/chip.asc
test/mystorm/flipflop/chip.bin
test/mystorm/flipflop/chip.blif

Hatim Kanchwala

@hatimak

hello! i have published slides https://speakerdeck.com/hatimak/edsac-museum-on-fpga

please have a look :)

sandipbhuyan

@sandipsandy_twitter

Hello I am sandip bhuyan from India Wants to work with your organization in GSoC 2018

Hatim Kanchwala

@hatimak

Hello @sandipsandy_twitter! This room is dedicated for the EDSAC Museum project under GSoC 2017. I’d be happy to help with that. If you are looking for participating with FOSSi under GSoC 2018 then your queries will be better answered in the Lobby room, which you are already part of ;)

Where communities thrive

People

Repo info

Activity