librecores/gsoc-museum-edsac

• the initial design of unit logic modules is ready. top level modules are also almost complete. a few trivial verilog-specific issues remain to be ironed before proceeding for synthesis.

• the documentation, especially the “big picture” one pointed out by @jeremybennett during last call is coming up well. i am preparing diagrams currently to better convey ideas. most of the documentation, along with diagrams, are in handwritten form in my notebook (and i am afraid my handwriting is illegible enough to make the notes cryptic for everyone other than me :P). once diagrams are ready i will be formally preparing a proper documentation (better than the markdown we have right now, will probably check out Sphinx like @wallento has for OpTiMSoC). the documentation is turning out well as a byproduct of my rather nightmar-ish engagement with the topic of timing and alignment of orders and numbers (more on this in the next point). conventionally, documentation is dealt with at the end of a gsoc project, bt in this case i’d like to offer two reasons to substantiate my decision - first, i anyway have to study the machine in depth to make the FPGA replica so it’d be nice to simultaneously document it, and second, with documentation available to everyone (including mentors), they can understand the machine and will be then better equipped to offer feedback on my work.

• nightmar-ish situation with timing and alignment of orders. this is where i am kind of stuck and has slowed down progress. quite a lot of issues i had when i reported earlier in the second week of june have been sorted out (that happened by repeated reading of documents and very fundamental step-by-step analysis, a mitigation strategy mentioned in the risk register). currently, there are still some issues in understanding multiplication operations, and most importantly, the boot sequence of EDSAC - the starting state and initial order loading. i am dealing with it following the same mitigation strategy of falling back to very fundamental step-by-step analysis, but i am afraid this will slow me down. i will be taking corrective measures later on to put us back on course.

• i have access to Bill’s repository of EDSAC documents (thanks to him for kindly sharing it). i firmly believe that i can glean from it enough information to pass through this timing/alignment issues. that is why i haven’t sent out a mail to Bill yet. if i had proceeded to writing to him, it would have probably taken 4-5 times the size of this entire message! quite a few of my issues i was going to raise in that email have been squashed after many hand drawn diagrams and hours of logical arguments with myself. if i have your permission i’d like to take time to try to figure this out myself. if the time taken jeopardises the project in any way i will be the first to seek out help and put it back on track.

please let me know if you have any questions. i will keep you posted with updates on the timing/alignment issue.

PS - if you wish to peruse my hand written notes, i’d be happy to send snaps over to you.