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Hatim Kanchwala
@hatimak
it’s been some time since i have posted updates, so here’s what i’d like to report
Hatim Kanchwala
@hatimak
  • the initial design of unit logic modules is ready. top level modules are also almost complete. a few trivial verilog-specific issues remain to be ironed before proceeding for synthesis.

  • the documentation, especially the “big picture” one pointed out by @jeremybennett during last call is coming up well. i am preparing diagrams currently to better convey ideas. most of the documentation, along with diagrams, are in handwritten form in my notebook (and i am afraid my handwriting is illegible enough to make the notes cryptic for everyone other than me :P). once diagrams are ready i will be formally preparing a proper documentation (better than the markdown we have right now, will probably check out Sphinx like @wallento has for OpTiMSoC). the documentation is turning out well as a byproduct of my rather nightmar-ish engagement with the topic of timing and alignment of orders and numbers (more on this in the next point). conventionally, documentation is dealt with at the end of a gsoc project, bt in this case i’d like to offer two reasons to substantiate my decision - first, i anyway have to study the machine in depth to make the FPGA replica so it’d be nice to simultaneously document it, and second, with documentation available to everyone (including mentors), they can understand the machine and will be then better equipped to offer feedback on my work.

  • nightmar-ish situation with timing and alignment of orders. this is where i am kind of stuck and has slowed down progress. quite a lot of issues i had when i reported earlier in the second week of june have been sorted out (that happened by repeated reading of documents and very fundamental step-by-step analysis, a mitigation strategy mentioned in the risk register). currently, there are still some issues in understanding multiplication operations, and most importantly, the boot sequence of EDSAC - the starting state and initial order loading. i am dealing with it following the same mitigation strategy of falling back to very fundamental step-by-step analysis, but i am afraid this will slow me down. i will be taking corrective measures later on to put us back on course.

  • i have access to Bill’s repository of EDSAC documents (thanks to him for kindly sharing it). i firmly believe that i can glean from it enough information to pass through this timing/alignment issues. that is why i haven’t sent out a mail to Bill yet. if i had proceeded to writing to him, it would have probably taken 4-5 times the size of this entire message! quite a few of my issues i was going to raise in that email have been squashed after many hand drawn diagrams and hours of logical arguments with myself. if i have your permission i’d like to take time to try to figure this out myself. if the time taken jeopardises the project in any way i will be the first to seek out help and put it back on track.

please let me know if you have any questions. i will keep you posted with updates on the timing/alignment issue.

PS - if you wish to peruse my hand written notes, i’d be happy to send snaps over to you.

PPS - should i have sent this update via email? if that makes things better, i’ll resort to sending updates only through email
Jeremy Bennett
@jeremybennett
@hatimak Thanks for the update. Can we move our call this week to Wednesday or Thursday? I'm out of the office on Tuesday. Thanks
@wallento I'm a bit out of my depth with @hatimak 's issue with timing and alignment. Are you able to offer any advice on this.
Hatim Kanchwala
@hatimak
@jeremybennett sure. any of wed or thur is fine according to your convenience. i’ll make myself available :)
just gently reminding - first evaluations are due mon onwards upto fri
could you please also share your view on point 2 and 4? :)
Jeremy Bennett
@jeremybennett
@hatimak Could we do 9am UK time on Wednesday (I have another call at 10am). I think that would be 1:30pm your time. By points 2 and 4, do you mean the bullet points above?
I shall complete the evaluation after our call on Wednesday. Hopefully @wallento will be able to join us. Will you post the hangout link here?
Stefan Wallentowitz
@wallento
yep, i will join
sorry, I had so much stuff to handle the last two weeks
I will have a read of the missed messages this afternoon
Stefan Wallentowitz
@wallento
Thanks again, will look at the details now
Stefan Wallentowitz
@wallento
@hatimak, can you point me to some code?
Stefan Wallentowitz
@wallento
sorry, I feel I just missed some pieces, lets spin me up during the call tomorrow!
Stefan Wallentowitz
@wallento
Hi
Sorry, I just received a call I have to pick up my baby from day care because he is sick
Stefan Wallentowitz
@wallento
ah, I still had the old call in my calendat
Hatim Kanchwala
@hatimak
hello
for the last two days, broadband connection was severely disrupted in my area. ISP technicians said there was some issue with the cables itself. connectivity restroed just this morning.
sorry @wallento there was a delay in replying to your texts owing to connectivity issues. i sent a text message to @jeremybennett last night updating him with my connectivity issues.
@jeremybennett @wallento we have a call scheduled on wed 28 july 9am (UK time). i’ll post the hangouts link here
@hatimak Could we do 9am UK time on Wednesday (I have another call at 10am). I think that would be 1:30pm your time. By points 2 and 4, do you mean the bullet points above?
@jeremybennett yes bullet points 2 and 4 above
@hatimak, can you point me to some code?
Hatim Kanchwala
@hatimak
@wallento i have all the code i have written hosted at the github repo you created https://github.com/librecores/gsoc-museum-edsac/
IMHO, the issue with timing may be better understood by looking at the logic diagrams on which the code is based
this is a link bill shared with me once. all his observations and diagrams are there - http://www.billp.org/ccs/Edsac/simulation.php
there is also a link to list of signals on the same page
Hatim Kanchwala
@hatimak
i have downloaded these diagrams and have been annotating them for the past couple of days. was doing this as part of the mitigation strategy i proposed - fundamental, step-by-step analysis
and as a product of those efforts, i am preparing a “grand timing” diagram of sorts to get an overview of all signals and relative alignments
both of this is WIP
sneak peek of “grand timing diagram” - https://pasteboard.co/dsXVaByL.png
Hatim Kanchwala
@hatimak
tl;dr - my suggestion would be to browse the code in conjunction with the logic diagrams from bill (on which part of the code is based)
@wallento please let me know any questions you have, i will be happy to discuss. connectivity is hopefully restored permanently now
Hatim Kanchwala
@hatimak
@jeremybennett i have submitted my part of the first evaluations
*evaluation~s~
sorry i meant*evaluation with a strikethorugh s
google tells me that my responses are automatically shared with FOSSi
thanks a lot for having shared your responses over the last call. here are mine -
first communication - between feb 27 and mar 20 (i dripped my first mail on mar 9)
ow often do i interact with mentor - twice a month (our once every two weeks Hangouts). have discounted gitter communications that happen on need basis
*how often
comm channel - IRC/group, video chat, priv email, list, blog
rate quality of interactions with mentor - excellent (5/5)
Hatim Kanchwala
@hatimak
responsiveness of mentor - moderate (3/5). you had said at the start of the project that you’d be busy.
i am happy to change the feedback if you would like me to (google allows resubmitting the form before deadline)
Stefan Wallentowitz
@wallento
no, please not, we are happy to get your feedback, but we highly encourage you to be open from the heart
Hatim Kanchwala
@hatimak
there was a question “what is your favourite part of participating in GSoC?” i have written a lengthy response to them which i will be including as blog post under a broader title “my experience with open source"