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  • Nov 09 2021 11:42
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    dependabot-preview[bot] on maven

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    dependabot-preview[bot] on maven

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Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Hi @oleg-nenashev I remember there was a doc shared regarding idea for jenkins plugin (embedded-sig) in gitter channel . I couldnt find it . Can you please provide me with the link if you remember
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Thanks
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Hi @oleg-nenashev
in repect to https://twitter.com/zipcpu/status/1176087197700820992 , should we add more things to our docker image ? https://github.com/librecores/docker-images
Oleg Nenashev
@oleg-nenashev
replied in Twitter
thanks!
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Yes , should we add it ?
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
@oleg-nenashev Recently I had been busy, but can we discuss on improving the existing yosys integration as I see , a lot of people responded to it on twitter , so I can work on to make it useful to other projects.
Oleg Nenashev
@oleg-nenashev
:+1:
This week is impossible for me, but we could do something on Oct 2 or 4
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Okay! That seems fine.
Oleg Nenashev
@oleg-nenashev
@/all My draft slides for ORCONF this year: https://speakerdeck.com/onenashev/whats-new-in-librecores-ci-orconf-2019 . There are still few hrs before the presentation, please let me know if you want something to be changed
Ghost
@ghost~5910ddcfd73408ce4f5dfa87
ok, mine is here:
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Hey @stffrdhrn @oleg-nenashev Nice presentations ! I saw Hacktoberfest slide , do you think we should raise tickets for it ?
Oleg Nenashev
@oleg-nenashev
@Nancy-Chauhan I already started doing so, more to come. If you have something in mind, just create them
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Yes @oleg-nenashev! Thank you ! I will look into this weekend :) do/ will i have to get access to put labels of hackoctoberfest ?
Oleg Nenashev
@oleg-nenashev
@Nancy-Chauhan I can gove you triage permissions so that you can do it. Will update permissions tomorrow
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
cool
Oleg Nenashev
@oleg-nenashev
@Nancy-Chauhan I reconfigured https://github.com/orgs/librecores/teams/librecores-ci-contributors so now you should have Triage permissions in all LCCI repositories
Oleg Nenashev
@oleg-nenashev
Also created https://github.com/librecores/ci.librecores.org so that we can start splitting SaaS and the Jenkins master repo
I think I will start the new repo in K8s right away
Will likely create a repo for the Helm chart later
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
oh Wow !
So we are thinking to move towards kubernetes

@Nancy-Chauhan I reconfigured https://github.com/orgs/librecores/teams/librecores-ci-contributors so now you should have Triage permissions in all LCCI repositories

Thanks Oleg !

Oleg Nenashev
@oleg-nenashev
K8s for our own infra at least
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Hi @oleg-nenashev are we good with aws now ? so that we can migrate openrisc to have running example
in that case , can i now send PR to or1k-marrochino to have yosys ( if now our jenkins work properly )
Oleg Nenashev
@oleg-nenashev
@Nancy-Chauhan AWS is kinda stable, but I still need to add a bit more resources to the instance. Good news is that I got access so that I can proceed with it
Akhil singh
@akhilsingh05_twitter
Hey guys, i looked at work you are doing. I have good knowledge of concepts related to advanced computer architecture like tomasulo's algorithm, exploiting parallelism etc. I have experience of coding in verilog for FPGA and using different synthesis tools like Xilinx, yosys(open source), i want to dive deep into new things like jenkins, docker, Kubernetes etc. Please let me know as how to start contributing into this and learn at the same time.
Oleg Nenashev
@oleg-nenashev
@akhilsingh05_twitter Hi, thanks for the interest! Currently I am creating newbie-friendly issues in LibreCores CI for Hacktoberfest: https://github.com/search?q=org%3Alibrecores+is%3Aissue+is%3Aopen+label%3Ahacktoberfest . it could be a good starting point
Akhil singh
@akhilsingh05_twitter
Thanks for responding. I will take a look at them.
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Hey @stffrdhrn @oleg-nenashev @akhilsingh05_twitter , I have been working on issue librecores/librecores-pipeline-lib#16 , here I am having some syntax errors ( verilog) : https://ci.librecores.org/job/Projects/job/OpenRISC/job/or1k_marocchino/view/change-requests/job/PR-16/2/console
@akhilsingh05_twitter , It would be great if you can help me with this : we had the similar issue in other project : openrisc/mor1kx#90
Akhil singh
@akhilsingh05_twitter
@Nancy-Chauhan Hey, i have changed one thing in the code and it is working fine for me now with no error.
1.png
Akhil singh
@akhilsingh05_twitter
@Nancy-Chauhan Error was coming because yosys does not support (synopsys|synthesis) parallel_case. So, as mentioned here: https://github.com/YosysHQ/yosys/blob/master/frontends/verilog/verilog_lexer.l . Now when that type of comments are used if you see line 369 in above link it will return TOK_SYNOPSYS_PARALLEL_CASE which is unexpected thus giving error. This error can be solved if instead of comment we write it in form of attribute. I did that and error got resolved.
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Yes thats true ! @akhilsingh05_twitter
But i guess we have to remove it from many files if I want to include fpu too
Akhil singh
@akhilsingh05_twitter
@Nancy-Chauhan @oleg-nenashev Adding comment after case is not the right way as done here: https://github.com/openrisc/mor1kx/pull/90/commits/cf13f5e811f62a8c267f879e9ec294acff0ecf5a . Though it will remove error and can also sometime fail as well, it is needed to convert those comments to attribute.
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Yes @akhilsingh05_twitter you got it right
Can you make a PR with the changes ? Will be quite good . Thanks for helping out
Akhil singh
@akhilsingh05_twitter
@Nancy-Chauhan What is fpu and there is need to replace that comment with attribute not remove it. For me it is working when i write it in attribute form
Can you tell which repository because if i identified correctly there are atleast two which have this error.
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
I meant pfpu_marocchino and also https://github.com/openrisc/or1k_marocchino/tree/master/rtl/verilog all files here
Akhil singh
@akhilsingh05_twitter
@Nancy-Chauhan Okay, will do it
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Thanks a lot @akhilsingh05_twitter
So I want to include : https://github.com/openrisc/or1k_marocchino/blob/master/or1k_marocchino.core#L39 and https://github.com/openrisc/or1k_marocchino/blob/master/or1k_marocchino.core#L7 all verilog files for yosys synthesis , and so I want these files dont have syntax errors !