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Ghost
@ghost~5b7e36e3d73408ce4fa5848d
So we are thinking to move towards kubernetes

@Nancy-Chauhan I reconfigured https://github.com/orgs/librecores/teams/librecores-ci-contributors so now you should have Triage permissions in all LCCI repositories

Thanks Oleg !

Oleg Nenashev
@oleg-nenashev
K8s for our own infra at least
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Hi @oleg-nenashev are we good with aws now ? so that we can migrate openrisc to have running example
in that case , can i now send PR to or1k-marrochino to have yosys ( if now our jenkins work properly )
Oleg Nenashev
@oleg-nenashev
@Nancy-Chauhan AWS is kinda stable, but I still need to add a bit more resources to the instance. Good news is that I got access so that I can proceed with it
Akhil singh
@akhilsingh05_twitter
Hey guys, i looked at work you are doing. I have good knowledge of concepts related to advanced computer architecture like tomasulo's algorithm, exploiting parallelism etc. I have experience of coding in verilog for FPGA and using different synthesis tools like Xilinx, yosys(open source), i want to dive deep into new things like jenkins, docker, Kubernetes etc. Please let me know as how to start contributing into this and learn at the same time.
Oleg Nenashev
@oleg-nenashev
@akhilsingh05_twitter Hi, thanks for the interest! Currently I am creating newbie-friendly issues in LibreCores CI for Hacktoberfest: https://github.com/search?q=org%3Alibrecores+is%3Aissue+is%3Aopen+label%3Ahacktoberfest . it could be a good starting point
Akhil singh
@akhilsingh05_twitter
Thanks for responding. I will take a look at them.
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Hey @stffrdhrn @oleg-nenashev @akhilsingh05_twitter , I have been working on issue librecores/librecores-pipeline-lib#16 , here I am having some syntax errors ( verilog) : https://ci.librecores.org/job/Projects/job/OpenRISC/job/or1k_marocchino/view/change-requests/job/PR-16/2/console
@akhilsingh05_twitter , It would be great if you can help me with this : we had the similar issue in other project : openrisc/mor1kx#90
Akhil singh
@akhilsingh05_twitter
@Nancy-Chauhan Hey, i have changed one thing in the code and it is working fine for me now with no error.
1.png
Akhil singh
@akhilsingh05_twitter
@Nancy-Chauhan Error was coming because yosys does not support (synopsys|synthesis) parallel_case. So, as mentioned here: https://github.com/YosysHQ/yosys/blob/master/frontends/verilog/verilog_lexer.l . Now when that type of comments are used if you see line 369 in above link it will return TOK_SYNOPSYS_PARALLEL_CASE which is unexpected thus giving error. This error can be solved if instead of comment we write it in form of attribute. I did that and error got resolved.
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Yes thats true ! @akhilsingh05_twitter
But i guess we have to remove it from many files if I want to include fpu too
Akhil singh
@akhilsingh05_twitter
@Nancy-Chauhan @oleg-nenashev Adding comment after case is not the right way as done here: https://github.com/openrisc/mor1kx/pull/90/commits/cf13f5e811f62a8c267f879e9ec294acff0ecf5a . Though it will remove error and can also sometime fail as well, it is needed to convert those comments to attribute.
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Yes @akhilsingh05_twitter you got it right
Can you make a PR with the changes ? Will be quite good . Thanks for helping out
Akhil singh
@akhilsingh05_twitter
@Nancy-Chauhan What is fpu and there is need to replace that comment with attribute not remove it. For me it is working when i write it in attribute form
Can you tell which repository because if i identified correctly there are atleast two which have this error.
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
I meant pfpu_marocchino and also https://github.com/openrisc/or1k_marocchino/tree/master/rtl/verilog all files here
Akhil singh
@akhilsingh05_twitter
@Nancy-Chauhan Okay, will do it
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Thanks a lot @akhilsingh05_twitter
So I want to include : https://github.com/openrisc/or1k_marocchino/blob/master/or1k_marocchino.core#L39 and https://github.com/openrisc/or1k_marocchino/blob/master/or1k_marocchino.core#L7 all verilog files for yosys synthesis , and so I want these files dont have syntax errors !
So Please send PR in the repository or1k_marocchino , correcting it
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Please let me know if you are block somewhere for this PR
Akhil singh
@akhilsingh05_twitter
@Nancy-Chauhan I am getting this: remote: Permission to openrisc/or1k_marocchino.git denied.
fatal: unable to access 'https://github.com/openrisc/or1k_marocchino.git/': The requested URL returned error: 403
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Are you trying to push code ?
Akhil singh
@akhilsingh05_twitter
Yes
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Okay , just clone it and then send changes with PR
Akhil singh
@akhilsingh05_twitter
@Nancy-Chauhan here is PR: openrisc/or1k_marocchino#17. Sorry for late response was having dinner.
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
That is alsolutely cool ! @akhilsingh05_twitter ! Thanks for the PR
I will have a look and will let you know
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
I have commented out the changes @akhilsingh05_twitter
Akhil singh
@akhilsingh05_twitter
@Nancy-Chauhan If it is okay i will change all the files which have similar issue by tomorrow.
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Cool @akhilsingh05_twitter ! Please also go through the comments also .
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Hey @akhilsingh05_twitter are u working on openrisc/or1k_marocchino#17 ?
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Hey @olofk @oleg-nenashev, I am willing to work on olofk/serv#8 , do you think it is good idea to keep it here . Can you look into this
Oleg Nenashev
@oleg-nenashev
@Nancy-Chauhan Yeah, I think having issues in the repos directly is a good thing
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
Hey @akhilsingh05_twitter I think your PR got merged lately , but are u working on other changes in code as well ? I will raise a ticket for it today
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
hey @oleg-nenashev , @stffrdhrn and I observed that last run of https://ci.librecores.org/job/Projects/job/OpenRISC/job/or1k_marocchino/ was 14 days . cant we have done it periodically ( more frequently ) and also @stffrdhrn wanted to trigger ( re - run
) the build, but I guess we are not able to build it . Can you help with this
Oleg Nenashev
@oleg-nenashev
@Nancy-Chauhan you should have permission to run the build. @stffrdhrn has no permission IIRC, because he did not log in into the system at the time when I was granting permissions. Can grant permissions later today
Ghost
@ghost~5b7e36e3d73408ce4fa5848d
@oleg-nenashev @stffrdhrn In that case :( I am currently not with my laptop for a few days. Will do it when I will return back !
Olof Kindgren
@olofk

Hey all,

I'm planning to build a container for a workshop and want to base it on the lcci images. I don't know shit about docker so I might need some hand holding :)

Olof Kindgren
@olofk
I have absolutely no idea what I'm doing right now :)
@Nancy-Chauhan @Nancy-Chauhan @oleg-nenashev I want to make some changes to how FuseSoC is installed in the base image. Can I make a local version of that image and test it on my machine somehow?
Olof Kindgren
@olofk
Tried rebuilding the base image now but get E: The method driver /usr/lib/apt/methods/https could not be found.
I have a vague memory of seeing this before on a ubuntu system
Olof Kindgren
@olofk
Which programs in the librecores base image needs python2? Would be great to drop that if not needed