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    Nazerke Turtayeva
    @NazerkeT
    I have rerun the build and separately run make at the Makefile. Actually this is how RISCV_GCC_OPTS look now: RISCV_GCC_OPTS ?= -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -march=rv64gc -Wa,-march=rv64gc_zbb_zbe_zbp_zbs -mno-riscv-attribute -O2
    Jonathan Balkind
    @Jbalkind
    if you run which riscv64-unknown-elf-gcc does it point to the correct one with bitmanip?
    Nazerke Turtayeva
    @NazerkeT
    Hi there! @Jbalkind I have found out my problem! It turned out that I have forgotten to build the ariane with vlt first(. Now I have added bit_extension.sv to Flist.ariane, Blender.yml, rebuilt openpiton, rebuilt ariane sim, then run dhrystone. But after minutes of run it failed with max_cycles error, so I gave increased value to -max_cycles flag and rerun. Nevertheless, it is running for over a 1.5 hour, is this okay? It seems that I have missed some crucial point. Could you help, please?
    Jonathan Balkind
    @Jbalkind
    sounds like you might have a bug if it's running for that long
    it might be better to remove the max_cycles and instead get the waveform to view in gtkwave
    from the shorter simulation
    Nazerke Turtayeva
    @NazerkeT
    okay, I see, I will look for
    Jonathan Balkind
    @Jbalkind
    you'll probably also want to objdump the diag.exe (if there isn't already a diag.dump)
    to see what the assembly is
    also, when you run the simulation, in the sims.log before the sim prints start, could you double check that it did successfully find the test to run?
    Nazerke Turtayeva
    @NazerkeT
    hmm, diag.dump seems dumped correctly, many instuctions exist there as of mini blocks, till the point when run had failed with max_cycles exceeded.
    Nazerke Turtayeva
    @NazerkeT
    Also, I did not see any rvb instructions
    Jonathan Balkind
    @Jbalkind
    yeah I'm not certain if objdump will show you the rvb instructions or not
    but you could still break regular ariane functionality with your changes ;
    you should be able to look at the pc trace log from ariane to see what it was executing
    does it keep printing as the simulation runs? or does it look like the core has frozen?
    Nazerke Turtayeva
    @NazerkeT

    you should be able to look at the pc trace log from ariane to see what it was executing

    okay, I will search for it, I guess most possibly i get wrong with my decoder

    does it keep printing as the simulation runs? or does it look like the core has frozen?

    it keeps printing as the simulation runs, then after 7 minutes reports following: .... TILE0 noc2 flit raw: 0x0000000000000000
    750000250 : Simulation -> (terminated by reaching max cycles = 1500000)

    For now, I have not noticed any frozen behaviour
    Jonathan Balkind
    @Jbalkind
    ok then you should look at the PC trace from ariane
    and compare that with the dump
    sajalgoyal
    @sajalgoyal
    Hello all
    This is Sajal Goyal, Mtech VLSI, IIIT-B and I am willing to contribute.
    My skillset includes: RTL, ASIC, FPGA, verilog, system-verilog, verification, Digital, STA, C and DS.
    Kindly guide me for the same.
    qaziullah
    @qaziullah
    Hello all,
    qaziullah
    @qaziullah
    I am trying to run NVDLA on FPGA and I need help with that. Can I get any help from here?
    Jonathan Balkind
    @Jbalkind
    hi @qaziullah, sure
    which FPGA do you have?
    Jonathan Balkind
    @Jbalkind
    the way that I set this up in the past was using the AXI memory controller we have
    I connected that to a Xilinx AXI crossbar IP and connected NVDLA to that crossbar too
    and then added an axi-lite device to program NVDLA's config registers
    qaziullah
    @qaziullah

    @Jbalkind Thank you for showing interest in helping me.
    First of all, I am new in this field so I may sometimes (or most of the time)
    will ask questions that may seem trivial to you.
    I hope you'll bear with me.

    For now, I have Altera DE-10 nano (with cyclone V SOC, dual-core Arm cortex A9 (HPS)).
    But if it is not good enough, I can get a decent altera FPGA board.

    I am following a thesis work of SHENBAGARAMAN RAMAKRISHNAN(https://lup.lub.lu.se/student-papers/search/publication/9007070). Right now, I have generated Verilog files from GitHub. I am trying to make an IP of NVDLA core from those files.
    While compiling the Verilog files in Quartus, I am getting errors with $RollPLI being
    not synthesizable (System function is not supported for synthesis). What should I do?
    Jonathan Balkind
    @Jbalkind
    wait so you're not trying to use openpiton?
    Jonathan Balkind
    @Jbalkind
    if you're just trying to use NVDLA in general rather than with OpenPiton, I'd suggest asking in the lobby channel
    Rishub
    @rishubn
    hi all. I am new to openpiton + ariane and a little confused about the debug workflow. I've built and ran the helloworld.c simulation and see the correct output on fake uart.log. I want to take a look at the execution starting from the bootloader and first instructions. How can I go about that? (gdb, qemu, spike ?)
    Jonathan Balkind
    @Jbalkind
    @rishubn it depends on your setup
    if you're not using verilator, ariane outputs a trace of the instructions it commits
    depending on your simulator you can add simulator-specific arguments to get a waveform out
    and sims.log already prints a lot of information about what's going on in the memory system
    we don't have the mechanism for co-sim with spike mainly because it wouldn't be deterministic for multicore
    someone asked the other day, I think on the google group (worth checking out if you're just getting started), about connecting gdb
    it's not something we've done but I think some of the boilerplate is there in the codebase
    generally that's not the mechanism we'd be using for debug
    Rishub
    @rishubn
    @Jbalkind I see thanks. Yes, I saw that gdb post and was also wondering how to get that set up. Could you possibly share more details on that? I'm playing with a dual core system (but one of the cores is strictly used for DMA only) so I do not think there would be an determinism issues. And using verilator
    Jonathan Balkind
    @Jbalkind
    as I said in my post, I'm not entirely sure of the details
    I believe some people have used the jtag-vpi library in the past for JTAG (not in openpiton but for other designs) to then connect to openocd and gdb
    we have the JTAG pins just sitting there in the design so I think connecting them to that would probably work
    you can take a look at Ariane's testbenches for how they hook up the JTAG to connect to spike too
    if you're looking into it I can give some general pointers but it's not something I know a ton about
    you might also like to make use of our zulip https://openpiton.zulipchat.com/ where we could set up a thread for it
    Rishub
    @rishubn
    Ah perfect, thanks!