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  • Oct 21 2019 19:20
    salmansheikh opened #10
  • Jul 27 2019 15:28
    apaj opened #9
  • Feb 18 2019 14:46

    codelec on master

    fix link (compare)

  • Feb 13 2019 02:45
    kai413629305 opened #8
  • Jan 01 2019 05:52

    codelec on master

    newer jars on maven restore nor… (compare)

  • Dec 16 2018 05:34

    codelec on master

    use older chisel3 and chisel-io… (compare)

  • Jul 15 2018 12:04

    codelec on master

    [common][rv32_1stage] use chise… (compare)

  • Jun 15 2018 08:59
    codelec closed #4
  • Jun 14 2018 18:37

    codelec on master

    [common] remove cloneType in fa… [1stage] modify imports to incl… [2stage] modify imports to incl… and 4 more (compare)

  • Jun 03 2018 10:06

    codelec on master

    [jenkins] add librecores-ci bui… (compare)

  • Jun 03 2018 10:05

    codelec on tilelink2_fpga

    [jenkins] add librecores-ci bui… (compare)

  • Jun 03 2018 09:51

    codelec on tilelink2_fpga

    [jenkins] checkout only after i… (compare)

  • Jun 03 2018 09:43

    codelec on tilelink2_fpga

    [common] use build.sbt instead … [common] use sbt-launch.jar for… (compare)

  • Jun 03 2018 09:18

    codelec on master

    [common] use sbt-launch.jar for… (compare)

  • Jun 03 2018 08:27

    codelec on master

    [common] use build.sbt instead … (compare)

  • Apr 28 2018 11:11

    codelec on master

    [rv32_1stage] changes to make u… [rv32_2stage] uarch diagram * x… [rv32_3stage] uarch diagram -> … and 2 more (compare)

  • Apr 19 2018 10:52

    codelec on tilelink2_fpga

    [librecores-ci] clean the binar… (compare)

  • Apr 19 2018 10:49

    codelec on tilelink2_fpga

    [librecores-ci] clean local ch… (compare)

  • Apr 19 2018 10:45

    codelec on tilelink2_fpga

    [librecores-ci] clean local ch… (compare)

  • Apr 19 2018 10:43

    codelec on tilelink2_fpga

    clean local changes in riscv-te… (compare)

Peter Aaser
@PeterAaser
oh, might be different in chisel 2
but I think you can just use RegInit( Vec(List.fill(n)(0.U(32.W))) )
just be careful that you dont do it the other way around, or you'll get a combinatoric circuit
at least in chisel3
it's a VHDL tier flaw, no idea why it's allowed
eric86103
@eric86103
hello I'm new to riscv and I just run the riscv-sodor. but unfourtunately, I could not find the "tracer data" in the sim results after I type "make run-emulator". Does anybody know how to get the stats report? Thanks!
Christopher Celio
@ccelio
I think that may only exist on a separate branch for the in-class lab version. It was very fragile.
kuanforml
@kuanforml
hello every i'm new to riscv-sodor. i want to run my own benchmark located in ${SODOR_DIR}/riscv-tests/build/benchmarks (benchmarks compiled by riscv-toolchains), however, after i run "make run-bmarks-test" in ${SODOR_DIR}/emulator/rv32_3stage, it just ran the global benchmarks (located in ${SODOR_DIR}/install). How can i run my custom benchmarks? Thanks!
eric86103
@eric86103
@ccelio thanks.... so do you know how to add tracer in the master branch?
Christopher Celio
@ccelio
eric86103
@eric86103
wow! thanks I will try it!
kuanforml
@kuanforml
@ccelio hello I have cloned the branch you posed above. however I failed to compile the emulator for many times. Do you know how to compile successfully?
kritik bhimani
@codelec
@qqttrr to get familiar with the syntax start with librecores/master. Only 3stage in master works with sync memory i.e. single cycle delay to read out from the memory. librecores/tilelink2_fpga has the 3stage modified to work with memory/IO that can take any number of cycles. The pipeline gets stalled until then. For your use case you need to modify 3stage in tilelink2_fpga branch to expect the reply within fixed n cycles since you plan to use an SRAM. I made short-sighted error there of not including caches in the design since most cores would ship with tightly coupled caches
@kuanforml can you post the error
kuanforml
@kuanforml
@codelec Oh, I have successfully compiled the emulator, and the compile error was due to the wrong version of java(8.0 required).
kuanforml
@kuanforml

@codelec However, I have encounter the other problem...
this branch provides a custom benchmark template in ${SODOR_DIR}/test/custom-bmarks/mix.c
When I used ''printf'' function in mix.c and ran the makefile, the following error emerged.

#include <stdio.h>
int main(void)
{
        // Write your code here
        int a = 0;
        a = 1 + 5;
        printf("1");
        return 0;
}

error:
riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -mcmodel=medany -std=gnu99 -O0 -fno-common -fno-builtin-printf -Wall -c mix.c -o mix.o
mix.c: In function 'main':
mix.c:5:6: warning: variable 'a' set but not used [-Wunused-but-set-variable]
int a = 0;
^
riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -mcmodel=medany -std=gnu99 -O0 -fno-common -fno-builtin-printf -Wall -DASSEMBLY=1 -c crt.S -o crt.o
riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -T link.ld -static -nostdlib -nostartfiles -lgcc mix.o crt.o -o mix.riscv
mix.o: In function .L0 ': mix.c:(.text+0x24): undefined reference toprintf'
collect2: error: ld returned 1 exit status
Makefile:25: recipe for target 'mix.riscv' failed
make: *
[mix.riscv] Error 1
rm crt.o mix.o**

Then, I modified the Makefile.

CC=riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32
OBJDUMP=riscv64-unknown-elf-objdump
CFLAGS=-mcmodel=medany -std=gnu99 -O0 -fno-common -fno-builtin-printf -Wall
#LDFLAGS=-static -nostdlib -nostartfiles -lgcc
#Remove the flag -nostdlib
LDFLAGS=-static  -nostartfiles -lgcc

PROGRAMS=mix
EXECUTABLES=$(addsuffix .riscv,$(PROGRAMS))
DUMPS=$(addsuffix .dump,$(PROGRAMS))
OUTFILES=$(addsuffix .out,$(PROGRAMS))

And it turned out
/home/kuan/test/lib/gcc/riscv64-unknown-elf/7.2.0/libgcc.a(_clz.o): ABI is incompatible with that of the selected emulation:
target emulation elf64-littleriscv' does not matchelf32-littleriscv'
/home/kuan/test/lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /home/kuan/test/lib/gcc/riscv64-unknown-elf/7.2.0/libgcc.a(_clz.o)
/home/kuan/test/lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/bin/ld: mix.riscv(.text): relocation "__sprint_r+0x0 (type R_RISCV_CALL)" goes out of range
/home/kuan/test/lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/bin/ld: /home/kuan/test/lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/lib/libc.a(lib_a-vfprintf.o): file class ELFCLASS64 incompatible with ELFCLASS32
/home/kuan/test/lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/bin/ld: final link failed: File in wrong format
collect2: error: ld returned 1 exit status
Makefile:26: recipe for target 'mix.riscv' failed
make: * [mix.riscv] Error 1
rm crt.o mix.o

Do you know how to fix it? Thx!

kritik bhimani
@codelec
If you scroll back in the chat history you will find my post on how to compile custom.c
kuanforml
@kuanforml

@ccelio
oh, I can compile now, and I'm able to use objdump to dump .out file.
However, after running

./emulator +loadmem=../../custom.riscv

the emulator couldn't stop and just kept running. I don't know what this problem is, do you know how to fix it?

kuanforml
@kuanforml

Oh, my custom benchmark, Makefile, and dumped file are attached below.
Custom Benckmark:
http://tpcg.io/KMi9H9
Makefile:

CC=riscv64-unknown-linux-gnu-gcc -march=rv32i -mabi=ilp32
OBJDUMP=riscv64-unknown-elf-objdump
CFLAGS=-mcmodel=medany -std=gnu99 -O0 -fno-common -fno-builtin-printf -Wall
#LDFLAGS=-static -nostdlib -nostartfiles -lgcc
#Remove the flag -nostdlib
LDFLAGS=-static  -nostartfiles -lgcc

PROGRAMS=sha256
EXECUTABLES=$(addsuffix .riscv,$(PROGRAMS))
DUMPS=$(addsuffix .dump,$(PROGRAMS))
OUTFILES=$(addsuffix .out,$(PROGRAMS))

all: $(EXECUTABLES)

run-riscv: $(OUTFILES)

dump: $(DUMPS)

%.out: %.riscv
        spike --isa=rv32i -l $< &> $@

%.dump: %.riscv
        $(OBJDUMP) -D $< > $@

%.riscv: %.o crt.o link.ld
        $(CC) -T link.ld $(LDFLAGS) $< crt.o -o $@

%.o: %.S
        $(CC) $(CFLAGS) -D__ASSEMBLY__=1 -c $< -o $@

%.o: %.c
        $(CC) $(CFLAGS) -c $< -o $@

clean:
        rm -f *.o *.riscv *.dump *.out
                                                              35,1-8        Bot

Dumped file:
http://tpcg.io/aFH9m4

Christopher Celio
@ccelio
you'd have to look at the output from the simulation to see what's going on, and what it is infinite looping on
kuanforml
@kuanforml
Thank you for your reply!
So, do my code and Makefile(i.e. the way I compile my code) result in the problem?
And can I find the problem in the file dumped by the objdump? Thanks!!
I have read the content of the file dumped by the objdump, and it seemed to be robust, so I want to know where I could find the problem.
kritik bhimani
@codelec
You need to write tohost address with exit code
gxlong1983
@gxlong1983
Does anyone know why the width of the source register rs1 is 52bit? The picture below is from hwacha instruction sets.
image.png
Peter Aaser
@PeterAaser
It's the top bits
so the width can be anything above 54 (so I'd guess 64)
Just guessing based on what you posted though
Peter Aaser
@PeterAaser
Does anyone know where I can find a grammar for RISC-V? Stuff like all pseudoOps and their semantics
kuanforml
@kuanforml
@ccelio And how can I write tohost address and what is the exit code ?
Thanks!!
maybe your program is large enough to overwrite the tohost address with program contents instead of leaving it blank
@kuanforml can you post the contents of "sha256.h"
the end sequence will be something like this
Cyc=      11353 Op1=[0x80001708] Op2=[0xfffff8f8] W[W,13= 0x80001000]   Mem[0: R:0x00000000 W:0x00000000] PC= 0x8000170c    addi    a3, a3, -1800
Cyc=      11354 Op1=[0x00000000] Op2=[0x00000001] W[W,14= 0x00000001]   Mem[0: R:0x13000000 W:0x80001a34] PC= 0x80001710    ori     a4, a0, 1
Cyc=      11355 Op1=[0x00000000] Op2=[0x00000000] W[W,15= 0x00000000]   Mem[0: R:0x00000093 W:0x00000000] PC= 0x80001714    li      a5, 0
Cyc=      11356 Op1=[0x80001000] Op2=[0x00000000] W[_, 0= 0x80001000]   Mem[0: R:0x00000000 W:0x00000001] PC= 0x80001718    sw      a4, 0(a3)
Cyc=      11357 Op1=[0x80001000] Op2=[0x00000004] W[_, 4= 0x80001004]   Mem[0: R:0x00000000 W:0x00000000] PC= 0x8000171c    sw      a5, 4(a3)
Cyc=      11358 Op1=[0x00000000] Op2=[0x00000000] W[W, 0= 0x80001724]   Mem[2: R:0x00000093 W:0x00000000] PC= 0x80001720  J j       pc + 0x0
Cyc=      11359 Op1=[0x00000000] Op2=[0x00000000] W[W, 0= 0x80001724]   Mem[2: R:0x00000093 W:0x00000000] PC= 0x80001720  J j       pc + 0x0
try custom.c example that i posted above
kritik bhimani
@codelec
this tohost address is polled frequently by fesvr
xuhaoee
@xuhaoee
where to download 'spike-dasm]'?
The link 'https://github.com/riscv/riscv-isa-run' in README cannot be found...
Cassiel-girl
@Cassiel-girl
which riscv implement using minimum fpga lut resource?
Divya Shah
@divyashah98
Does anyone have soft copy of riscv reader by patterson and waterman ?
Cassiel-girl
@Cassiel-girl
how to compile riscv-gcc gcc command binary to run on rocket?
Zhiyuan Shao
@MrShawCode
hi all, I have downloaded the riscv-sodor from https://github.com/librecores/riscv-sodor, and then switch to the tilelink2_fpga branch (I want to play sodor on my artix FPGA board).
but during making, it yields lots of errors during building the Top.v, as follows:
cd /home/zhiyuan/work/riscv-sodor-readyfpga && java -Xmx4096M -Xss8M -XX:MaxPermSize=128M -jar /home/zhiyuan/work/riscv-sodor-readyfpga/sbt-launch.jar "project rv32_1stage" "run -td emulator/rv32_1stage/generated-src"
OpenJDK 64-Bit Server VM warning: ignoring option MaxPermSize=128M; support was removed in 8.0
[info] Loading project definition from /home/zhiyuan/work/riscv-sodor-readyfpga/project
[info] Loading settings from build.sbt ...
[info] Set current project to riscv-sodor-readyfpga (in build file:/home/zhiyuan/work/riscv-sodor-readyfpga/)
[info] Set current project to rv32_1stage (in build file:/home/zhiyuan/work/riscv-sodor-readyfpga/)
[info] Compiling 10 Scala sources to /home/zhiyuan/work/riscv-sodor-readyfpga/common/target/scala-2.11/classes ...
[warn] there were two deprecation warnings; re-run with -deprecation for details
[warn] there were 100 feature warnings; re-run with -feature for details
[warn] two warnings found
[info] Done compiling.
[info] Compiling 6 Scala sources to /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/target/scala-2.11/classes ...
[info] Packaging /home/zhiyuan/work/riscv-sodor-readyfpga/common/target/scala-2.11/common_2.11-3.0.jar ...
[info] Done packaging.
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv321stage/core.scala:22:8: not found: object freechips
[error] import freechips.rocketchip.config.

[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/core.scala:24:30: not found: type Parameters
[error] class CoreIo(implicit val p: Parameters) extends Bundle
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/core.scala:26:14: could not find implicit value for parameter conf: Common.SodorConfiguration
[error] val imem = new MemPortIo(p(xprlen))
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/core.scala:27:14: could not find implicit value for parameter conf: Common.SodorConfiguration
[error] val dmem = new MemPortIo(p(xprlen))
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/core.scala:28:24: could not find implicit value for parameter conf: Common.SodorConfiguration
[error] val ddpath = Flipped(new DebugDPath())
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/core.scala:29:24: could not find implicit value for parameter conf: Common.SodorConfiguration
[error] val dcpath = Flipped(new DebugCPath())
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/core.scala:32:24: not found: type Parameters
[error] class Core(implicit p: Parameters) extends Module
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv321stage/cpath.scala:15:8: not found: object freechips
[error] import freechips.rocketchip.config.

[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/cpath.scala:40:27: not found: type Parameters
[error] class CtlPath(implicit p: Parameters) extends Module
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv321stage/dpath.scala:16:8: not found: object freechips
[error] import freechips.rocketchip.config.

[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/dpath.scala:36:27: not found: type Parameters
[error] class DatPath(implicit p: Parameters) extends Module
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/cpath.scala:30:31: not found: type Parameters
[error] class CpathIo(implicit val p: Parameters) extends Bundle()
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/cpath.scala:32:25: could not find implicit value for parameter conf: Common.SodorConfiguration
[error] val
Can someone tell me what should I do to achieve my goal (play sodor on FPGA board)?
Are the problems I have encountered during the building the compatibility problems from chisel2 to chisel3?
claford-v-lawrence
@claford-v-lawrence
Anyone got any idea how to import this into idea?
For some reason, when I mark the src directory as sources root, I cannot import Chisel3 anymore