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  • Sep 27 06:11
    abignail commented #9
  • Sep 27 06:10
    abignail commented #9
  • Sep 27 02:34
    abignail commented #9
  • Jun 20 03:54
    Tianhang-Cheng opened #13
  • Jun 17 14:08
    Tianhang-Cheng closed #12
  • Jun 17 14:08
    Tianhang-Cheng commented #12
  • Jun 17 08:45
    Tianhang-Cheng opened #12
  • Jun 17 08:31
    Tianhang-Cheng commented #11
  • Oct 30 2020 04:53
    dhxsy1994 closed #11
  • Oct 19 2020 10:06
    dhxsy1994 edited #11
  • Oct 19 2020 10:06
    dhxsy1994 opened #11
  • Oct 21 2019 19:20
    salmansheikh opened #10
  • Jul 27 2019 15:28
    apaj opened #9
  • Feb 18 2019 14:46

    codelec on master

    fix link (compare)

  • Feb 13 2019 02:45
    kai413629305 opened #8
  • Jan 01 2019 05:52

    codelec on master

    newer jars on maven restore nor… (compare)

  • Dec 16 2018 05:34

    codelec on master

    use older chisel3 and chisel-io… (compare)

  • Jul 15 2018 12:04

    codelec on master

    [common][rv32_1stage] use chise… (compare)

  • Jun 15 2018 08:59
    codelec closed #4
  • Jun 14 2018 18:37

    codelec on master

    [common] remove cloneType in fa… [1stage] modify imports to incl… [2stage] modify imports to incl… and 4 more (compare)

Stefan Wallentowitz
@wallento
It's only icarus currently, which is okay if you have verilog only, system verilog is an issue
Christopher Celio
@ccelio
@wallento speaking of Verilator, are hierarchical references not possible? can I not write code in a test bench that peeks/reads some signal lower down in the hierarchy?
Stefan Wallentowitz
@wallento
@ccelio yes, that works
I use it in my testbenches too
Christopher Celio
@ccelio
thanks!
I was shown the verilator manual and it says it doesn't support "hierarchical references", which I cold've sworn it does.
Christopher Celio
@ccelio
today I learned I can't read system verlog, lol
Stefan Wallentowitz
@wallento
There are contradictory statements in the manual I see now
bset
I mean
I think the first is informative about the synthesis subset, which is kind of common among all tools
But it says pretty clearly it only supports this subset and explicitly excludes hierarchical
Only to introduce that right below :)
I will open a ticket to fix this..
Stefan Wallentowitz
@wallento
@ccelio SV for design or for verification? If it was the former, you should give the latter a try.. :)
Christopher Celio
@ccelio
yah, I've done so much design in chisel using hand-crafted (and mostly C++) tethered test-harnesses to do my "verification". I'm now dealing with how do I actually do an honest-to-god attempt at verifying Chisel IP using actual verification engineers. I definitely have a lot to learn!
Xing GUO
@vgxbj
Oops, Stefan you are here too, Hello again! Hi all, I just build the riscv-sodor, and find a little bug, don't know if it's my own problem ... whatever, I just add one line using std::string and all work well
See ucb-bar/riscv-sodor#37
Stefan Wallentowitz
@wallento
hey, that was fixed in the librecores version too
I think you should use that
Xing GUO
@vgxbj
Thanks a lot😀 Sorry for my ignorance ... :)
Stefan Wallentowitz
@wallento
no, I agree thats confusing
Christopher Celio
@ccelio
god i need more time to review pull requests. :( Sorry about that.
OnchipUIS
@onchipuis
Hi. I want to know if debug module is working on sodor processors. I can't follow the DebugDPath or DebugCPath inside core. Thank you!
kritik bhimani
@codelec
@onchipuis debug module is working on sodor but the current implementation is hacky and uses some non-standard address to ease resetting the core. DebugDPath and DebugCPath is for control signals that would be used to control data path and control path respectively which may be required for halting/breakpoint and other debug features. As of now both of them are used just to access the register file of core(tilelink2_fpga branch). In master branch I have removed them to ease understanding.
halting/breaking and other needed debug features have not yet been implemented
kritik bhimani
@codelec
main functionality of current debug module is to load data into memory and probe it when required by the debug host. this was done to avoid using magic features like readmemh(verilator) and make it easier to get it working on fpga
OnchipUIS
@onchipuis
Ok! Thank you very much!
Christopher Celio
@ccelio
have you guys ever tried IntelliJ? I'm trying to see if I can get it set up for my own stuff, using (http://blog.edmondcote.com/2018/04/using-intellij-as-rocketchip-ide.html) as inspiration.
it looks like it would really cut down on the confusion of what the dependencies and project hierarchy is doing.
kritik bhimani
@codelec
i have modified the uarch diagrams yesterday, they are not supposed to replace to the chisel design sources and are just for reference purpose so you will not find every signal in those diagrams.
Stefan Wallentowitz
@wallento
great, thanks!
Peter Aaser
@PeterAaser
Has anyone here used sodor along with PYNQs?
We'll be using them for a course this fall, was hoping to use sodor for the coursework
Christopher Celio
@ccelio
yah, @codelec has demonstrated Sodor on a PYNQ board. Not sure on the status of that though. WHen I tried it the challenge was loading a binary of your choice into its memory.
Peter Aaser
@PeterAaser
We have a framework in chisel 2 for it actually. The pynq is frustratingly close to a nice user experience...
Honestly if it was up to me I'd run the whole course on emulators exclusively, but the damage done by VHDL is hard to undo.
kritik bhimani
@codelec
@PeterAaser you can ping me if you have any issue with using sodor on pynq
the last time i tried all the benchmarks and isa tests were passing on pynq
it shouldn't take much time for you to try it on pynq .. instructions given in repo are complete and known to work. Loading all isa tests and bmarks on pynq is automated
kritik bhimani
@codelec
please ensure the binary is compiled with -march=rv32i -mabi=ilp32 as flag to compiler .. if a binary works on zynqsimtop emulator it should work on pynq
kritik bhimani
@codelec
@ccelio did you try it on emulator
Christopher Celio
@ccelio
@codelec super sorry, I haven't had a chance to try your latest efforts yet. My PYNQ sits on my desk shaming me every day.
Peter Aaser
@PeterAaser
@codelec awesome, I'll let you know if I run into trouble
kritik bhimani
@codelec
custom.c
#include "util.h"
int main(){
    setStats(1);
    int a = 45;
    int b = 99;
    printf(" add:%d sub:%d mul:%d\n",a+b,b-a,a*b);
    printf("hello world\n");
    setStats(0);
}
riscv64-unknown-elf-gcc -Iriscv-tests/env -Iriscv-tests/benchmarks/common -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -march=rv32i -mabi=ilp32 -o custom.riscv custom.c riscv-tests/benchmarks/common/syscalls.c riscv-tests/benchmarks/common/crt.S -static -nostdlib -nostartfiles -lm -lgcc -T riscv-tests/benchmarks/common/test.ld