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  • Jun 20 03:54
    Tianhang-Cheng opened #13
  • Jun 17 14:08
    Tianhang-Cheng closed #12
  • Jun 17 14:08
    Tianhang-Cheng commented #12
  • Jun 17 08:45
    Tianhang-Cheng opened #12
  • Jun 17 08:31
    Tianhang-Cheng commented #11
  • Oct 30 2020 04:53
    dhxsy1994 closed #11
  • Oct 19 2020 10:06
    dhxsy1994 edited #11
  • Oct 19 2020 10:06
    dhxsy1994 opened #11
  • Oct 21 2019 19:20
    salmansheikh opened #10
  • Jul 27 2019 15:28
    apaj opened #9
  • Feb 18 2019 14:46

    codelec on master

    fix link (compare)

  • Feb 13 2019 02:45
    kai413629305 opened #8
  • Jan 01 2019 05:52

    codelec on master

    newer jars on maven restore nor… (compare)

  • Dec 16 2018 05:34

    codelec on master

    use older chisel3 and chisel-io… (compare)

  • Jul 15 2018 12:04

    codelec on master

    [common][rv32_1stage] use chise… (compare)

  • Jun 15 2018 08:59
    codelec closed #4
  • Jun 14 2018 18:37

    codelec on master

    [common] remove cloneType in fa… [1stage] modify imports to incl… [2stage] modify imports to incl… and 4 more (compare)

  • Jun 03 2018 10:06

    codelec on master

    [jenkins] add librecores-ci bui… (compare)

  • Jun 03 2018 10:05

    codelec on tilelink2_fpga

    [jenkins] add librecores-ci bui… (compare)

  • Jun 03 2018 09:51

    codelec on tilelink2_fpga

    [jenkins] checkout only after i… (compare)

kritik bhimani
@codelec
please ensure the binary is compiled with -march=rv32i -mabi=ilp32 as flag to compiler .. if a binary works on zynqsimtop emulator it should work on pynq
kritik bhimani
@codelec
@ccelio did you try it on emulator
Christopher Celio
@ccelio
@codelec super sorry, I haven't had a chance to try your latest efforts yet. My PYNQ sits on my desk shaming me every day.
Peter Aaser
@PeterAaser
@codelec awesome, I'll let you know if I run into trouble
kritik bhimani
@codelec
custom.c
#include "util.h"
int main(){
    setStats(1);
    int a = 45;
    int b = 99;
    printf(" add:%d sub:%d mul:%d\n",a+b,b-a,a*b);
    printf("hello world\n");
    setStats(0);
}
riscv64-unknown-elf-gcc -Iriscv-tests/env -Iriscv-tests/benchmarks/common -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -march=rv32i -mabi=ilp32 -o custom.riscv custom.c riscv-tests/benchmarks/common/syscalls.c riscv-tests/benchmarks/common/crt.S -static -nostdlib -nostartfiles -lm -lgcc -T riscv-tests/benchmarks/common/test.ld
spike --isa=RV32I custom.riscv
cd emulator/<config>/
make emulator
./emulator +loadmem=../../custom.riscv
custom.riscv works on zynqsimtop
kritik bhimani
@codelec
@PeterAaser any suggestions on how the layout could be made better. Sodor does not implement interrupts. Exceptions are supported to give brief insight into fault handling i.e. "what do you do when something happens that the product is not designed for?"
in other words what should sodor do when it gets a misaligned load address should it give back some junk value or should it fail safely
Peter Aaser
@PeterAaser
Does anyone have any good sources for test programs for RV32IM?
MilesZhao
@MilesZhao
Hi there, I new to Sodor core. I am doing homework at my school. I have a question to set the bypassing configurations. I want to how to set "EXE->EXE(forward output of EXE to the input of EXE)".
I know that the code should in dpath.scala and cpath.scala
nikhilnimmagadda
@nikhilnsv_twitter
@MilesZhao did you find the solution for the posted question..i'm also looking for the same
Nikolai
@qqttrr
Hello everyone! We begin implementing a minion core. The core will have custom ISRs, instruction SRAM with firmware loaded in, several read memory ports, and Tilelink interface to DRAM. For this we decided to modify sodor. There are 3 branches of sodor: ucb-bar, librecores/master and librecores/tilelink2_fpga. Which one would you suggest as the starting point for our case? Thanks in advance!
Christopher Celio
@ccelio
Probably librecores/master? I think Kritik's work is the most up-to-date.
Peter Aaser
@PeterAaser
Anyone here got a list of pseudo-ops for risc-v?
writing a parser for my test suite and I need to desugar gcc output
Cassiel-girl
@Cassiel-girl
who has lookup chisel code?
Christopher Celio
@ccelio
Cassiel-girl
@Cassiel-girl
how generate testbench that can be used by third-party eda tools???
Peter Aaser
@PeterAaser
Anyone know what "tail" desugars to?
egads
Cassiel-girl
@Cassiel-girl
how to create and initilize reg vec in chisel2?
Peter Aaser
@PeterAaser
there is a section on it
sec
Peter Aaser
@PeterAaser
oh, might be different in chisel 2
but I think you can just use RegInit( Vec(List.fill(n)(0.U(32.W))) )
just be careful that you dont do it the other way around, or you'll get a combinatoric circuit
at least in chisel3
it's a VHDL tier flaw, no idea why it's allowed
ericwu13
@ericwu13
hello I'm new to riscv and I just run the riscv-sodor. but unfourtunately, I could not find the "tracer data" in the sim results after I type "make run-emulator". Does anybody know how to get the stats report? Thanks!
Christopher Celio
@ccelio
I think that may only exist on a separate branch for the in-class lab version. It was very fragile.
kuanforml
@kuanforml
hello every i'm new to riscv-sodor. i want to run my own benchmark located in ${SODOR_DIR}/riscv-tests/build/benchmarks (benchmarks compiled by riscv-toolchains), however, after i run "make run-bmarks-test" in ${SODOR_DIR}/emulator/rv32_3stage, it just ran the global benchmarks (located in ${SODOR_DIR}/install). How can i run my custom benchmarks? Thanks!
ericwu13
@ericwu13
@ccelio thanks.... so do you know how to add tracer in the master branch?
Christopher Celio
@ccelio
ericwu13
@ericwu13
wow! thanks I will try it!
kuanforml
@kuanforml
@ccelio hello I have cloned the branch you posed above. however I failed to compile the emulator for many times. Do you know how to compile successfully?
kritik bhimani
@codelec
@qqttrr to get familiar with the syntax start with librecores/master. Only 3stage in master works with sync memory i.e. single cycle delay to read out from the memory. librecores/tilelink2_fpga has the 3stage modified to work with memory/IO that can take any number of cycles. The pipeline gets stalled until then. For your use case you need to modify 3stage in tilelink2_fpga branch to expect the reply within fixed n cycles since you plan to use an SRAM. I made short-sighted error there of not including caches in the design since most cores would ship with tightly coupled caches
@kuanforml can you post the error
kuanforml
@kuanforml
@codelec Oh, I have successfully compiled the emulator, and the compile error was due to the wrong version of java(8.0 required).
kuanforml
@kuanforml

@codelec However, I have encounter the other problem...
this branch provides a custom benchmark template in ${SODOR_DIR}/test/custom-bmarks/mix.c
When I used ''printf'' function in mix.c and ran the makefile, the following error emerged.

#include <stdio.h>
int main(void)
{
        // Write your code here
        int a = 0;
        a = 1 + 5;
        printf("1");
        return 0;
}

error:
riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -mcmodel=medany -std=gnu99 -O0 -fno-common -fno-builtin-printf -Wall -c mix.c -o mix.o
mix.c: In function 'main':
mix.c:5:6: warning: variable 'a' set but not used [-Wunused-but-set-variable]
int a = 0;
^
riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -mcmodel=medany -std=gnu99 -O0 -fno-common -fno-builtin-printf -Wall -DASSEMBLY=1 -c crt.S -o crt.o
riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -T link.ld -static -nostdlib -nostartfiles -lgcc mix.o crt.o -o mix.riscv
mix.o: In function .L0 ': mix.c:(.text+0x24): undefined reference toprintf'
collect2: error: ld returned 1 exit status
Makefile:25: recipe for target 'mix.riscv' failed
make: *
[mix.riscv] Error 1
rm crt.o mix.o**

Then, I modified the Makefile.

CC=riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32
OBJDUMP=riscv64-unknown-elf-objdump
CFLAGS=-mcmodel=medany -std=gnu99 -O0 -fno-common -fno-builtin-printf -Wall
#LDFLAGS=-static -nostdlib -nostartfiles -lgcc
#Remove the flag -nostdlib
LDFLAGS=-static  -nostartfiles -lgcc

PROGRAMS=mix
EXECUTABLES=$(addsuffix .riscv,$(PROGRAMS))
DUMPS=$(addsuffix .dump,$(PROGRAMS))
OUTFILES=$(addsuffix .out,$(PROGRAMS))

And it turned out
/home/kuan/test/lib/gcc/riscv64-unknown-elf/7.2.0/libgcc.a(_clz.o): ABI is incompatible with that of the selected emulation:
target emulation elf64-littleriscv' does not matchelf32-littleriscv'
/home/kuan/test/lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /home/kuan/test/lib/gcc/riscv64-unknown-elf/7.2.0/libgcc.a(_clz.o)
/home/kuan/test/lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/bin/ld: mix.riscv(.text): relocation "__sprint_r+0x0 (type R_RISCV_CALL)" goes out of range
/home/kuan/test/lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/bin/ld: /home/kuan/test/lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/lib/libc.a(lib_a-vfprintf.o): file class ELFCLASS64 incompatible with ELFCLASS32
/home/kuan/test/lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/bin/ld: final link failed: File in wrong format
collect2: error: ld returned 1 exit status
Makefile:26: recipe for target 'mix.riscv' failed
make: * [mix.riscv] Error 1
rm crt.o mix.o

Do you know how to fix it? Thx!

kritik bhimani
@codelec
If you scroll back in the chat history you will find my post on how to compile custom.c
kuanforml
@kuanforml

@ccelio
oh, I can compile now, and I'm able to use objdump to dump .out file.
However, after running

./emulator +loadmem=../../custom.riscv

the emulator couldn't stop and just kept running. I don't know what this problem is, do you know how to fix it?

kuanforml
@kuanforml

Oh, my custom benchmark, Makefile, and dumped file are attached below.
Custom Benckmark:
http://tpcg.io/KMi9H9
Makefile:

CC=riscv64-unknown-linux-gnu-gcc -march=rv32i -mabi=ilp32
OBJDUMP=riscv64-unknown-elf-objdump
CFLAGS=-mcmodel=medany -std=gnu99 -O0 -fno-common -fno-builtin-printf -Wall
#LDFLAGS=-static -nostdlib -nostartfiles -lgcc
#Remove the flag -nostdlib
LDFLAGS=-static  -nostartfiles -lgcc

PROGRAMS=sha256
EXECUTABLES=$(addsuffix .riscv,$(PROGRAMS))
DUMPS=$(addsuffix .dump,$(PROGRAMS))
OUTFILES=$(addsuffix .out,$(PROGRAMS))

all: $(EXECUTABLES)

run-riscv: $(OUTFILES)

dump: $(DUMPS)

%.out: %.riscv
        spike --isa=rv32i -l $< &> $@

%.dump: %.riscv
        $(OBJDUMP) -D $< > $@

%.riscv: %.o crt.o link.ld
        $(CC) -T link.ld $(LDFLAGS) $< crt.o -o $@

%.o: %.S
        $(CC) $(CFLAGS) -D__ASSEMBLY__=1 -c $< -o $@

%.o: %.c
        $(CC) $(CFLAGS) -c $< -o $@

clean:
        rm -f *.o *.riscv *.dump *.out
                                                              35,1-8        Bot

Dumped file:
http://tpcg.io/aFH9m4

Christopher Celio
@ccelio
you'd have to look at the output from the simulation to see what's going on, and what it is infinite looping on
kuanforml
@kuanforml
Thank you for your reply!
So, do my code and Makefile(i.e. the way I compile my code) result in the problem?
And can I find the problem in the file dumped by the objdump? Thanks!!
I have read the content of the file dumped by the objdump, and it seemed to be robust, so I want to know where I could find the problem.
kritik bhimani
@codelec
You need to write tohost address with exit code
gxlong1983
@gxlong1983
Does anyone know why the width of the source register rs1 is 52bit? The picture below is from hwacha instruction sets.