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  • Jun 20 03:54
    Tianhang-Cheng opened #13
  • Jun 17 14:08
    Tianhang-Cheng closed #12
  • Jun 17 14:08
    Tianhang-Cheng commented #12
  • Jun 17 08:45
    Tianhang-Cheng opened #12
  • Jun 17 08:31
    Tianhang-Cheng commented #11
  • Oct 30 2020 04:53
    dhxsy1994 closed #11
  • Oct 19 2020 10:06
    dhxsy1994 edited #11
  • Oct 19 2020 10:06
    dhxsy1994 opened #11
  • Oct 21 2019 19:20
    salmansheikh opened #10
  • Jul 27 2019 15:28
    apaj opened #9
  • Feb 18 2019 14:46

    codelec on master

    fix link (compare)

  • Feb 13 2019 02:45
    kai413629305 opened #8
  • Jan 01 2019 05:52

    codelec on master

    newer jars on maven restore nor… (compare)

  • Dec 16 2018 05:34

    codelec on master

    use older chisel3 and chisel-io… (compare)

  • Jul 15 2018 12:04

    codelec on master

    [common][rv32_1stage] use chise… (compare)

  • Jun 15 2018 08:59
    codelec closed #4
  • Jun 14 2018 18:37

    codelec on master

    [common] remove cloneType in fa… [1stage] modify imports to incl… [2stage] modify imports to incl… and 4 more (compare)

  • Jun 03 2018 10:06

    codelec on master

    [jenkins] add librecores-ci bui… (compare)

  • Jun 03 2018 10:05

    codelec on tilelink2_fpga

    [jenkins] add librecores-ci bui… (compare)

  • Jun 03 2018 09:51

    codelec on tilelink2_fpga

    [jenkins] checkout only after i… (compare)

kritik bhimani
@codelec
try custom.c example that i posted above
this tohost address is polled frequently by fesvr
xuhaoee
@xuhaoee
where to download 'spike-dasm]'?
The link 'https://github.com/riscv/riscv-isa-run' in README cannot be found...
Cassiel-girl
@Cassiel-girl
which riscv implement using minimum fpga lut resource?
Divya Shah
@divyashah98
Does anyone have soft copy of riscv reader by patterson and waterman ?
Cassiel-girl
@Cassiel-girl
how to compile riscv-gcc gcc command binary to run on rocket?
Zhiyuan Shao
@MrShawCode
hi all, I have downloaded the riscv-sodor from https://github.com/librecores/riscv-sodor, and then switch to the tilelink2_fpga branch (I want to play sodor on my artix FPGA board).
but during making, it yields lots of errors during building the Top.v, as follows:
cd /home/zhiyuan/work/riscv-sodor-readyfpga && java -Xmx4096M -Xss8M -XX:MaxPermSize=128M -jar /home/zhiyuan/work/riscv-sodor-readyfpga/sbt-launch.jar "project rv32_1stage" "run -td emulator/rv32_1stage/generated-src"
OpenJDK 64-Bit Server VM warning: ignoring option MaxPermSize=128M; support was removed in 8.0
[info] Loading project definition from /home/zhiyuan/work/riscv-sodor-readyfpga/project
[info] Loading settings from build.sbt ...
[info] Set current project to riscv-sodor-readyfpga (in build file:/home/zhiyuan/work/riscv-sodor-readyfpga/)
[info] Set current project to rv32_1stage (in build file:/home/zhiyuan/work/riscv-sodor-readyfpga/)
[info] Compiling 10 Scala sources to /home/zhiyuan/work/riscv-sodor-readyfpga/common/target/scala-2.11/classes ...
[warn] there were two deprecation warnings; re-run with -deprecation for details
[warn] there were 100 feature warnings; re-run with -feature for details
[warn] two warnings found
[info] Done compiling.
[info] Compiling 6 Scala sources to /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/target/scala-2.11/classes ...
[info] Packaging /home/zhiyuan/work/riscv-sodor-readyfpga/common/target/scala-2.11/common_2.11-3.0.jar ...
[info] Done packaging.
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv321stage/core.scala:22:8: not found: object freechips
[error] import freechips.rocketchip.config.

[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/core.scala:24:30: not found: type Parameters
[error] class CoreIo(implicit val p: Parameters) extends Bundle
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/core.scala:26:14: could not find implicit value for parameter conf: Common.SodorConfiguration
[error] val imem = new MemPortIo(p(xprlen))
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/core.scala:27:14: could not find implicit value for parameter conf: Common.SodorConfiguration
[error] val dmem = new MemPortIo(p(xprlen))
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/core.scala:28:24: could not find implicit value for parameter conf: Common.SodorConfiguration
[error] val ddpath = Flipped(new DebugDPath())
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/core.scala:29:24: could not find implicit value for parameter conf: Common.SodorConfiguration
[error] val dcpath = Flipped(new DebugCPath())
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/core.scala:32:24: not found: type Parameters
[error] class Core(implicit p: Parameters) extends Module
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv321stage/cpath.scala:15:8: not found: object freechips
[error] import freechips.rocketchip.config.

[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/cpath.scala:40:27: not found: type Parameters
[error] class CtlPath(implicit p: Parameters) extends Module
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv321stage/dpath.scala:16:8: not found: object freechips
[error] import freechips.rocketchip.config.

[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/dpath.scala:36:27: not found: type Parameters
[error] class DatPath(implicit p: Parameters) extends Module
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/cpath.scala:30:31: not found: type Parameters
[error] class CpathIo(implicit val p: Parameters) extends Bundle()
[error] ^
[error] /home/zhiyuan/work/riscv-sodor-readyfpga/rv32_1stage/../src/rv32_1stage/cpath.scala:32:25: could not find implicit value for parameter conf: Common.SodorConfiguration
[error] val
Can someone tell me what should I do to achieve my goal (play sodor on FPGA board)?
Are the problems I have encountered during the building the compatibility problems from chisel2 to chisel3?
claford-v-lawrence
@claford-v-lawrence
Anyone got any idea how to import this into idea?
For some reason, when I mark the src directory as sources root, I cannot import Chisel3 anymore
Usman Zain
@usmnzen_twitter

executing make run-emulator produces the following error:

./emulator +max-cycles=30000 /home/usman/Documents/chisel-projects/riscv-sodor/install/riscv-tests/rv32ui-p-simple 3>&1 1>&2 2>&3 | /home/usman/Documents/chisel-projects/riscv-sodor/emulator/common/tracer.py > output/rv32ui-p-simple.out make[1]: *** [/home/usman/Documents/chisel-projects/riscv-sodor/emulator/common/Makefile.include:215: output/rv32ui-p-simple.out] Error 255 make[1]: Leaving directory '/home/usman/Documents/chisel-projects/riscv-sodor/emulator/rv32_1stage' make: *** [Makefile:102: emulator/rv32_1stage/generated-src/timestamp] Error 2

Any idea on what's causing this error?

Usman Zain
@usmnzen_twitter

The make run-emulator command is executing 1stage core. The output/rv32ui-p-simple.out file shows the following error:

*** FAILED *** (timeout) after 30000 cycles

sajalgoyal
@sajalgoyal
Hello all
This is Sajal Goyal, Mtech VLSI, IIIT-B and I am willing to contribute.
My skillset includes: RTL, ASIC, FPGA, verilog, system-verilog, verification, Digital, STA, C and DS.
Kindly guide me for the same.
Hessen Du
@dhxsy1994

The make run-emulator command is executing 1stage core. The output/rv32ui-p-simple.out file shows the following error:

*** FAILED *** (timeout) after 30000 cycles

my error is same as your, did you solved it ?

Usman Zain
@usmnzen_twitter
@dhxsy1994 I was unable to solve it on the ucberkeley version of the sodor core. I instead used the librecores/riscv-sodor fork which does not cause this error when not using the debug mode.
Hessen Du
@dhxsy1994
@usmnzen_twitter did your environment have any chisel toolchain installed? I tried succeed with g++8.3.0 and whole new virtual machine environment on 'cs152-sp20' branch. I can not find the failed reason.
Muhammad Salman Afzal
@muhammadsalmanafzal
Hey there, hope you are all doing well. I'm thinking of doing my final year project on RISCV. The area can be RISCV verification or ISP, Debug for the in-house generated bare-metal core. I have a made a core in Verilog supporting RV32IM and currently working on the F extension. So, I know a thing or two on the design part. Can anyone tell me which would be a better project complexity wise since I'm doing it all alone (due to certain conditions at our university), so, I don't want to take on something that is too hard to solve. Can anyone briefly tell me how to proceed in each case since both things will be new to me? Thanks.
Usman Zain
@usmnzen_twitter
@muhammadsalmanafzal what area did you decide for your fyp then?
Muhammad Salman Afzal
@muhammadsalmanafzal

@muhammadsalmanafzal what area did you decide for your fyp then?

For now, we have chosen verification, but we have yet to define the scope of it and what to do?

Muhammad Salman Afzal
@muhammadsalmanafzal
Since I'm getting started with Verification, can somebody tell me if the following is possible:
Make an end to end RISCV based verification enviroment such that it can verify (Functional) any core, bare-metal for starter implementing I-extension, in a way that with a few switch changes here and there like changing no. of bits (16, 32, 64), or piplelines(2,3,4,5,6...), optional F and other extensions, respective core can be verified.
For example, in my case, what I'm trying to do is (for starting point) make a bare-metal RV32I verification enviroment that can not only verify standard 5-stage pipeline but also, bare-metal cores of various pipelines(2, 3, 5...) and so on as it progresses.
I know its a very open-ended problem, but can anyone guide me how to get started? If there is any similar work present? I'll appreciate it. Thanks.
Saad Khalid
@Saad525
@muhammadsalmanafzal you can have a look at "riscv google dv" thats an open source risc v test generator and it also has capability to integrate your core into its environment.
Muhammad Salman Afzal
@muhammadsalmanafzal
@Saad525 but it requires some tools like Questa, Xcelium etc for working and I don't have any access to any of those. Do you know any way that I can run it without those? or maybe there is some way to run UVM 1.2 and SV on something other than the tools mentioned?
Saad Khalid
@Saad525
@muhammadsalmanafzal I think you are right. Other than the tools you mentioned, VCS supports UVM but its also proprietary. If you are using Verilator then maybe test environment like python based cocotb can serve your purpose.