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  • Sep 20 15:44
    zeeshanrafique23 commented #62
  • Sep 20 15:42
    zeeshanrafique23 opened #63
  • Sep 18 16:46
    zeeshanrafique23 commented #62
  • Sep 18 16:46
    zeeshanrafique23 commented #62
  • Sep 18 16:30
    olofk commented #62
  • Sep 18 16:12
    zeeshanrafique23 commented #62
  • Sep 18 15:56
    hakan-demirli opened #62
  • Sep 17 08:20
    olofk commented #61
  • Sep 16 23:50
    develone synchronize #61
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    develone commented #61
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Zeeshan Rafique
@zeeshanrafique23

There are some things we can improve in the core description file so that we don't need to repeat the same thing for all targets, but let's wait with that and start by just adding the mdu stuff to the targets we have tested

Sure.

Zeeshan Rafique
@zeeshanrafique23
Any other thing if I am missing?
Zeeshan Rafique
@zeeshanrafique23
CoreScore is an award-giving benchmark for FPGAs
@olofk Do you have something which hasn't owned an award?
Azamazing!
Olof Kindgren
@olofk
CoreScore hasn't won any awards. It gives awards :)
Leaving now. Back later tonight
Zeeshan Rafique
@zeeshanrafique23
Oh yes, kilocore club
Olof Kindgren
@olofk
Alright then! We now have M-extension support in SERV!!!
Olof Kindgren
@olofk
Unfortunately CI failed. I'll take a look
Oh, come on! There's a lint warning about the waiver file itself. Verilator complains that it doesn't end with a newline
I'll force-push a change before anyone notices
Passes CI and no one saw a thing
Zeeshan Rafique
@zeeshanrafique23
Yahoo Finally… RV32IM
Olof Kindgren
@olofk
@klasnordmark Doing some cleaning up of old SERV branches. Noticed we never pushed the initial openlane stuff for serv. Took the liberty to change a couple of things in your patch. Could you take a look and see that you're still ok with it before I push to main? It's on this branch https://github.com/olofk/serv/tree/openlane
It passes CI at least :)
Olof Kindgren
@olofk
Hmm.. think I found a bug when refreshing the riscv-formal support
Olof Kindgren
@olofk
Seems like it occurs when we have certain kind of CSR instructions followed by an instruction using a signed immediate
Zeeshan Rafique
@zeeshanrafique23
Are you talking about openlane branch or the main?
Olof Kindgren
@olofk
The bug is on both branches. I have a fix for it so it's not the end of the world but could be good to know. There hasn't been that many bugs in SERV and since this is such a minor thing I just think it's pretty neat that it was found by formal tools :)
And it looks like subservient was built without the CSR support so there's still a chance we taped out bug-free silicon
Zeeshan Rafique
@zeeshanrafique23
That’s great. :)
Klas Nordmark
@klasnordmark
Sure thing, I'll take a look when I get home. Didn't even see this tagging of mr until now... Something up with the gitter app
Klas Nordmark
@klasnordmark
should be fine I think?
Olof Kindgren
@olofk
Thanks @klasnordmark . I think it should be ok but wanted your blessing since I changed things in your patch
Olof Kindgren
@olofk
@klasnordmark In case you didn't see, I merged it some days ago
develone
@develone
@olofk I have a early Catboard by Dave Vanderbout. It has 100 MHz clock, a HX8K, 32Mb SDRAM, 4green leds,2 push button switches, a dip with 4 switches and 2 pmods and mounts on a RPi3B with a 40 pin connector. Where would I find the steps to get serv working on my catboard? I have icestorm, yosys, nextpnr, and verilator working on my RPi4B 4Gb. I was able to build ./build/servant_1.1.0/go_board-icestorm/servant_1.1.0.bin, ./build/servant_1.1.0/tinyfpga_bx-icestorm/servant_1.1.0.bin, and ./build/servant_1.1.0/icebreaker-icestorm/servant_1.1.0.bin.
develone
@develone
@olofk https://github.com/develone/icozip/blob/catzip/doc/Working-Software.pdf. Lifting step dwt by ZipCPU. I was interested in seeing if 16 cores would help.
develone
@develone
@olofk I use https://github.com/develone/catboard_yosys/blob/master/config_cat to program my catboard and https://github.com/develone/catboard_yosys/blob/master/reset_cat to reset it. I put these in /usr/local/bin on my RPi3B,
Olof Kindgren
@olofk
@develone You're well on your way already. I suggest starting with the basic servant SoC which just uses a single output pin that you can connect to a LED. Then you can add more advanced features after that. For your board, I think you can reuse the existing service top level and just add your pin constraints. I'll give a more detailed answer when I'm at the computer
develone
@develone
@olofk created a pull request in your repo to add data/catzip.pcf
develone
@develone
@olofk After several tries I was able to get servant_1.1.0/catzip-icestorm/servant_1.1.0.bin. This required changes to serv/servant.core an adding data/catzip.pcf. This sent un readable characters to minicom when I programmed the catboard. My Helloworld wworked ok at 115200 8N1.
develone
@develone
@olofk I pushed an update to pull request adding some documentation.
KinzaQamar
@KinzaQamar
Greetings @olofk
I wanted to ask if compressed extension support will be added in SERV , which way for the implementation of decoder consumes less hardware
1) Implement a separate decoder for "C" instrcutions
2) Add the implementation of the decoder into the decoder of SERV
Olof Kindgren
@olofk
@develone Thanks! I will take a look at it as soon as I can find the time. Been a bit too much lately. Sorry for keeping you hanging
@KinzaQamar Hmmm.. that's a good question. It would be cleaner if we could have a separate decoder but I think we need to make changes in several parts of the core, so it might not be possible.
For example, I think we need to make changes in serv_ctrl to allow to allow half-word alignment
KinzaQamar
@KinzaQamar
@olofk Yes we have to take care of half word alignment and pc incremental value (pc+2 when compressed)
Zeeshan Rafique
@zeeshanrafique23
@olofk What you think how should Kinza start compressed extension support for SERV, I and Kinza both are working to get this task done.
I introduced her with the basics overview of SERV. She is pretty confident to start
Zeeshan Rafique
@zeeshanrafique23
We are confused in a scenario, that if we have 1st instruction compressed and second instruction non-compressed(normal ins), then we have to concatenate the results of two addresses (PC=4 + PC=2). In this do we have to use a fifo or something else...? Need your help.
  eg.
               | 31               16 | 15             0 |  
  FIFO entry 0 | Instr 1 [15:0]      | Instr 0 [15:0]   |
  FIFO entry 1 | Instr 2 [15:0]      | Instr 1 [31:16]  |
Olof Kindgren
@olofk
Hi @zeeshanrafique23 and @KinzaQamar ! Awesome to see you are working on this. Good question about how to handle unaligned 32-bit instructions
Olof Kindgren
@olofk
Just thinking about this quickly I would probably do it something like this
  1. Fetch {instr1[15:0],instr0[15:0]} as an aligned 32-bit word (like you show in FIFO entry 0)
  2. After instr0 is completed we know that we don't need the lower 16 bits anymore so I would do a fetch to pull in instr1[31:16] in the lower 16 bits (so it looks like {instr1[15:0],instr1[31:16]}. Then I would send this swapped to the decoder so that it appears like instr1[31:0]
The downside of doing it like this is that we will fetch some instructions that we just throw away, but I think it will lead to the most compact implementation, and it might be better to add a separate prefetching unit if we care that much about memory accesses
Zeeshan Rafique
@zeeshanrafique23
Sounds promising.
@KinzaQamar could you please first draw this in waveforms, before getting hands-on on RTL. The scenario Olof just explained above.
KinzaQamar
@KinzaQamar
@olofk sounds like a deal ,
@zeeshanrafique23 Task Noted !
Zeeshan Rafique
@zeeshanrafique23
There are several RISC-V cores available which implements RV32IC so can we reuse their compressed decoder or we must implement our own?
@olofk
Olof Kindgren
@olofk
@zeeshanrafique23 If we find something we can reuse, then we should do that. Just make sure to check they are released under a compatible license