/hier[3:0]are a form of hierarchy. 2.
m4+name(..)is an instantiation of a multi-line macro using proof-of-concept notation. 3.
<>0is "natural alignment" meaning the numerical pipestage delta between current scope and referenced scope is zero. Also
>>1is "ahead by one" or "previous" (in same pipeline) and
<<1is "behind by one" or "next".
\$displayis an escaped reference in TLV context to SV
\SVare regions of TLV and SV code.
\SVregions are passed through SandPiper without processing. And yes, tlv_flow_lib makes heavy use of undocumented proof-of-concept M4 features. Learn the fundamentals before going there. You might find it insightful with each example you look at in Makerchip to compare the source code, the Nav-TLV code, and the "E"-"Show Verilog" code. Use available trainings rather than jumping into WARP-V and tlv_flow_lib. Learn MYTH cores before WARP-V. (https://github.com/stevehoover/RISC-V_MYTH_Workshop)
--compiler verilator. Try without this and let me know. I'll be in the midst of conducting a 5-day workshop starting soon, so I'll be a bit tied up. @ahadnagy , please keep an eye on discussions.
fpga-webserver. I've got a list of TL-Verilog project ideas here: https://github.com/stevehoover/TL-V_Projects.