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    Steve Hoover
    @stevehoover
    I don't have wishbone or AXI examples.
    develone
    @develone
    @stevehoover After commenting 'include "sqrt32.v" in top.sv. This is what I used "yosys -l simple.log -p 'synth_ice40 -blif top.blif -json top.json' top.sv clk_gate.v pseudo_rand.sv" This was the result SB_LUT4 66 . Thanks.
    mayank-kabra2001
    @mayank-kabra2001
    @stevehoover i was going through one of the processor (Shivani shah) in MYTH . All the processor was build in tlverilog and use of m4 was only in building assembly language program and for visualization . But when i looked at warp-v there is heavy use of m4 ... can you explain why ?? because we can build the same 5 stage processor in tlv also .
    Steve Hoover
    @stevehoover
    @mayank-kabra2001 WARP-V is highly parameterized using M4. E.g. you can configure # of stages, supported extensions, etc.
    develone
    @develone
    @stevehoover I have been trying to create a sdram module in tlv. "https://github.com/develone/sandpiper_test/blob/master/sdram/top.tlv". When I uncommnet line 50 the waveform becomes a red x. This is part a of count down counter that is needed to be set up, when the sdram needs refresh. How does the simulation in Makerchip still have values with a red x? On my system verilator fails no simulation. This is the link to "http://makerchip.com/sandbox/0n5fGhZkR/0r0h8y8#"? The only way I can see the pipe, is to clear the editor and paste the top.tlv that I downloaded. It should look like "https://github.com/develone/sandpiper_test/blob/master/sdram/top_trans.pdf".
    2 replies
    develone
    @develone
    @stevehoover There's a RPi w/ PCIe support. see youtube https://youtu.be/a-0PeuPINiQ which 4G. The cost is $90 + 35 for connection board. This would require "https://github.com/develone/sandpiper_test/tree/master/Time-Div-Mult" to combine the 4 1GB ethernets. This could be done with catboard or icoboard, compute module, and IO Board. See the 2 cm4 pdfs in "https://github.com/develone/sandpiper_test/tree/master/doc".
    develone
    @develone
    @stevehoover Dan Gisselquist (zipcpu) yesterday had a 2nd formal verification zoom meeting AXI-lite RAM. His repo is "https://github.com/ZipCPU/wb2axip". He has said many times that Xilinx AXI has bugs. I am not smart enough to know for sure. I have been trying to convince him to take a look at TL-V. His zipcpu is a 5 stage pipeline that is doing my DWT with mul & div in SB_LUT4 4209.
    1 reply
    mayank-kabra2001
    @mayank-kabra2001
    doubt .png
    @stevehoover can u explain why we have written |pipe in front of every variable as this variable is only in that pipeline . Also in #entry which is of 64 bits is compared with wr_index which is 32 bits . can u explain what does this entry means .. is it an infinite(means acc to our convenience) 64 arrays ???
    mayank-kabra2001
    @mayank-kabra2001
    doubt2.png
    what does this line means ///Decode: Extracting src reg fields//////// ?????
    develone
    @develone
    mayank-kabra2001 see TL-Verilog Reference Card at end of CODE-EXAMPLES.
    mayank-kabra2001
    @mayank-kabra2001
    Thanks a lot @develone i found ans to all my doubts .. except Still im not able to find what does #entry (i.e. Decode: Extracting src reg fields) does ????
    2 replies
    mayank-kabra2001
    @mayank-kabra2001
    and also i was going through the MYTH workshop and looked at one of the projects . At the top of the file i found this ... m4_include_lib(['https://raw.githubusercontent.com/stevehoover/RISC-V_MYTH_Workshop/c1719d5b338896577b79ee76c2f443ca2a76e14f/tlv_lib/risc-v_shell_lib.tlv']) .. can you please tell me what it does ????
    2 replies
    mayank-kabra2001
    @mayank-kabra2001
    and also what does this `BOGUS_USE($data1 $data2) means ????
    2 replies
    develone
    @develone
    @stevehoover How do you make this module axil2axis be part of TLV? see "http://makerchip.com/sandbox/00Rf2hWZG/0y8hrGX" & "https://github.com/develone/sandpiper_test/tree/master/axil2axi". Is this on the right path? Will the verilog at some point be removed?
    6 replies
    develone
    @develone
    @stevehoover The axi2xbar work might be at the right time. See "https://www.hackster.io/news/cva6-a-linux-capable-risc-v-cpu-299a40a5f871". zipcpu indicated they also had bugs. The warp-v can support 6 stages in RISC-V?
    1 reply
    develone
    @develone
    @stevehoover I tested "http://makerchip.com/sandbox/0J6f8hLX8/0AnhNxg#" "https://github.com/stevehoover/makerchip_examples/blob/master/flow_example_basejump_viz.tlv" in makerchip. Needed to comment line 93 m4+trans() in makerchip. Waveform works ok in makerchip. Sandpiper & verilator works okay see "https://github.com/develone/sandpiper_test/blob/master/BaseJump/waveform.png" Diagram fails in makerchip See "https://github.com/develone/sandpiper_test/blob/master/BaseJump/top_trans.pdf" Do you have more information on M4.?
    1 reply
    develone
    @develone
    @stevehoover the bitbucket appears to have moved to github: https://github.com/bespoke-silicon-group/basejump_stl
    develone
    @develone
    @stevehoover https://github.com/bespoke-silicon-group/basejump_stl/tree/master/bsg_misc The circular_ptr.v was getting an error on line 54 from bitbucket. ./sv_url_inc/bsg_circular_ptr.v:54: ERROR: syntax error, unexpected $undefined with yosys.
    develone
    @develone
    2 replies
    Steve Hoover
    @stevehoover
    I would debug that as a verilog bug, without regard to the tlv source.
    develone
    @develone
    @stevehoover What does this line 247 //m4+cpu_viz(@4) need? Do I need to install additional software. I cloned one of the students "https://github.com/AMITROY71/risc-v-myth-workshop-august-AMITROY71/blob/master/Day3_5/risc-v_solutions.tlv". In Makerchip it worked ok, but not with sandpiper. Can you provide some ideas on my revised design which I tried to document in "https://github.com/develone/sandpiper_test/blob/master/doc/axi.pdf". https://github.com/develone/sandpiper_test/tree/master/axil2axi I am trying to get some help at the gitter myhdl see my post to Alex Forencich.
    2 replies
    develone
    @develone
    @stevehoover see my notes "https://github.com/develone/sandpiper_test/blob/master/test-tlv/notes.txt" This works in Makerchip but now with sandpiper local. See the FATAL_ERROR(10) (PARSE-IDENT): File 'top.tlv' Line 247 (char 16).
    develone
    @develone
    @stevehoover can you explain the difference between Makerchip.com, sandpiper in the cloud and sandpiper local. Don't understand top.tlv & top.m4.
    Steve Hoover
    @stevehoover
    \viz_alpha is a new (alpha) debug feature that is not supported outside of the ide. You can delete that block of code outside of mc.
    Stay tuned for announcements @develone
    Shivam Awasthi
    @the-good-boy
    Hello! My name is Shivam Awasthi.. Can you please tell me what I should look into so that I can contribute to some projects in future? Thanks!
    Steve Hoover
    @stevehoover
    Hi @the-good-boy I saw that you mentioned fractalvalley in the lobby. The room for that is actually fpga-webserver. I've got a list of TL-Verilog project ideas here: https://github.com/stevehoover/TL-V_Projects.
    Shivam Awasthi
    @the-good-boy
    Thanks @stevehoover ! The resources mentioned in this look very interesting to me. I will look into them and then get back to you. Thank you so much!
    Deepak S
    @Deepak-suresh14
    @stevehoover even I would like to work on this
    Steve Hoover
    @stevehoover
    @Deepak-suresh14 @the-good-boy , you can use those pointers to get ramped up, and then let me know what interests you most.
    Deepak S
    @Deepak-suresh14
    @stevehoover yes sir definitely
    develone
    @develone
    @the-good-boy & @Deepak-suresh14 I am also trying to learn TLV. I have a C program that takes in a PGM image and computes the forward and inverse DWT. I currently have one instance of lifting_step.v, 2 instances of ram.v which are used as input & output buffers. In addition, I have an instance of signed2twoscomplement.v & one instance oneminuszero.v. These verilog files were created using MyHDL. Using a testbench in MyHDL I am comparing the output of C program to results of the Verilog. I think that this should convert to to TLV using the array example in Makerchip.com instead of the of the 2 instances of ram.v. One of the issues with array is that I have not been able to synthsize using Yosys. A pipe would be good for lifting_step since it takes several clks to obtain a Hi & Lo pass. See "https://github.com/develone/myhdl-relook/blob/master/transaction/lift_step.pdf"
    Harshita Gupta
    @harshitaaaaaa
    Hey, I am Harshita Gupta from Thapar University. I'm a full-stack Web Developer. I saw a project http://www.fractalvalley.net/ and I'm highly interested in contributing to this. Can you please guide me with this?
    Steve Hoover
    @stevehoover
    Harshita Gupta
    @harshitaaaaaa
    Yes @stevehoover I have gone through these TL-V_Projects but not through the 1st-CLaaS. I've chosen fractal-valley from TL-V_Projects only.
    Steve Hoover
    @stevehoover
    @harshitaaaaaa fractalvalley is created using 1st CLaaS. There are several aspects of the project. Is it the front-end development that interests you most? What are your background and skills?
    Harshita Gupta
    @harshitaaaaaa
    @stevehoover Yes sir, my major area of interest is front-end development. I am currently a second-year student. I want to learn and implement my skills, so I found this project interesting.
    Steve Hoover
    @stevehoover
    @harshitaaaaaa Do you have experience with React?
    Harshita Gupta
    @harshitaaaaaa
    @stevehoover Yes sir, I've learned react and currently focusing at making small projects with react. Currently I'm trying to make a whatsapp-clone using MERN stack.
    Steve Hoover
    @stevehoover
    Great, @harshitaaaaaa . I'd be happy to have you contribute. Fractalvally was a popular project that almost got traction several times. There are several student efforts that never saw the light of day, but would give you a good head start. You should be able to find links via the 1st CLaaS repo (following into the Mandelbrot readme).
    Harshita Gupta
    @harshitaaaaaa
    Thank You Sir, @stevehoover I'll have a look through the repo.
    Steve Hoover
    @stevehoover
    Great job, @mayank-kabra2001 with this blog post on Verilog vs. TLV: https://mayank-kabra2001.github.io/My-BlogPost/
    mayank-kabra2001
    @mayank-kabra2001
    Thanks a lot , Sir.
    develone
    @develone
    @stevehoover This is the cnd I am using to synthesise the array from Makerchip "yosys -l simple.log -p 'synth_ice40 -blif top.blif -json top.json' top.sv pseudo_rand.sv". See "https://github.com/develone/sandpiper_test/blob/master/array/simple.log".
    Steve Hoover
    @stevehoover
    @develone What's 'top.json'?
    develone
    @develone
    yosys creates the bilf and json files used by nextpnr to do the place and route. When it goes ok see https://github.com/develone/sandpiper_test/blob/master/test2/blinky.json
    Steve Hoover
    @stevehoover
    thx @develone