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    develone
    @develone
    @stevehoover I tested "http://makerchip.com/sandbox/0J6f8hLX8/0AnhNxg#" "https://github.com/stevehoover/makerchip_examples/blob/master/flow_example_basejump_viz.tlv" in makerchip. Needed to comment line 93 m4+trans() in makerchip. Waveform works ok in makerchip. Sandpiper & verilator works okay see "https://github.com/develone/sandpiper_test/blob/master/BaseJump/waveform.png" Diagram fails in makerchip See "https://github.com/develone/sandpiper_test/blob/master/BaseJump/top_trans.pdf" Do you have more information on M4.?
    1 reply
    develone
    @develone
    @stevehoover the bitbucket appears to have moved to github: https://github.com/bespoke-silicon-group/basejump_stl
    develone
    @develone
    @stevehoover https://github.com/bespoke-silicon-group/basejump_stl/tree/master/bsg_misc The circular_ptr.v was getting an error on line 54 from bitbucket. ./sv_url_inc/bsg_circular_ptr.v:54: ERROR: syntax error, unexpected $undefined with yosys.
    develone
    @develone
    2 replies
    Steve Hoover
    @stevehoover
    I would debug that as a verilog bug, without regard to the tlv source.
    develone
    @develone
    @stevehoover What does this line 247 //m4+cpu_viz(@4) need? Do I need to install additional software. I cloned one of the students "https://github.com/AMITROY71/risc-v-myth-workshop-august-AMITROY71/blob/master/Day3_5/risc-v_solutions.tlv". In Makerchip it worked ok, but not with sandpiper. Can you provide some ideas on my revised design which I tried to document in "https://github.com/develone/sandpiper_test/blob/master/doc/axi.pdf". https://github.com/develone/sandpiper_test/tree/master/axil2axi I am trying to get some help at the gitter myhdl see my post to Alex Forencich.
    2 replies
    develone
    @develone
    @stevehoover see my notes "https://github.com/develone/sandpiper_test/blob/master/test-tlv/notes.txt" This works in Makerchip but now with sandpiper local. See the FATAL_ERROR(10) (PARSE-IDENT): File 'top.tlv' Line 247 (char 16).
    develone
    @develone
    @stevehoover can you explain the difference between Makerchip.com, sandpiper in the cloud and sandpiper local. Don't understand top.tlv & top.m4.
    Steve Hoover
    @stevehoover
    \viz_alpha is a new (alpha) debug feature that is not supported outside of the ide. You can delete that block of code outside of mc.
    Stay tuned for announcements @develone
    Shivam Awasthi
    @the-good-boy
    Hello! My name is Shivam Awasthi.. Can you please tell me what I should look into so that I can contribute to some projects in future? Thanks!
    Steve Hoover
    @stevehoover
    Hi @the-good-boy I saw that you mentioned fractalvalley in the lobby. The room for that is actually fpga-webserver. I've got a list of TL-Verilog project ideas here: https://github.com/stevehoover/TL-V_Projects.
    Shivam Awasthi
    @the-good-boy
    Thanks @stevehoover ! The resources mentioned in this look very interesting to me. I will look into them and then get back to you. Thank you so much!
    Deepak S
    @Deepak-suresh14
    @stevehoover even I would like to work on this
    Steve Hoover
    @stevehoover
    @Deepak-suresh14 @the-good-boy , you can use those pointers to get ramped up, and then let me know what interests you most.
    Deepak S
    @Deepak-suresh14
    @stevehoover yes sir definitely
    develone
    @develone
    @the-good-boy & @Deepak-suresh14 I am also trying to learn TLV. I have a C program that takes in a PGM image and computes the forward and inverse DWT. I currently have one instance of lifting_step.v, 2 instances of ram.v which are used as input & output buffers. In addition, I have an instance of signed2twoscomplement.v & one instance oneminuszero.v. These verilog files were created using MyHDL. Using a testbench in MyHDL I am comparing the output of C program to results of the Verilog. I think that this should convert to to TLV using the array example in Makerchip.com instead of the of the 2 instances of ram.v. One of the issues with array is that I have not been able to synthsize using Yosys. A pipe would be good for lifting_step since it takes several clks to obtain a Hi & Lo pass. See "https://github.com/develone/myhdl-relook/blob/master/transaction/lift_step.pdf"
    Harshita Gupta
    @harshitaaaaaa
    Hey, I am Harshita Gupta from Thapar University. I'm a full-stack Web Developer. I saw a project http://www.fractalvalley.net/ and I'm highly interested in contributing to this. Can you please guide me with this?
    Steve Hoover
    @stevehoover
    Harshita Gupta
    @harshitaaaaaa
    Yes @stevehoover I have gone through these TL-V_Projects but not through the 1st-CLaaS. I've chosen fractal-valley from TL-V_Projects only.
    Steve Hoover
    @stevehoover
    @harshitaaaaaa fractalvalley is created using 1st CLaaS. There are several aspects of the project. Is it the front-end development that interests you most? What are your background and skills?
    Harshita Gupta
    @harshitaaaaaa
    @stevehoover Yes sir, my major area of interest is front-end development. I am currently a second-year student. I want to learn and implement my skills, so I found this project interesting.
    Steve Hoover
    @stevehoover
    @harshitaaaaaa Do you have experience with React?
    Harshita Gupta
    @harshitaaaaaa
    @stevehoover Yes sir, I've learned react and currently focusing at making small projects with react. Currently I'm trying to make a whatsapp-clone using MERN stack.
    Steve Hoover
    @stevehoover
    Great, @harshitaaaaaa . I'd be happy to have you contribute. Fractalvally was a popular project that almost got traction several times. There are several student efforts that never saw the light of day, but would give you a good head start. You should be able to find links via the 1st CLaaS repo (following into the Mandelbrot readme).
    Harshita Gupta
    @harshitaaaaaa
    Thank You Sir, @stevehoover I'll have a look through the repo.
    Steve Hoover
    @stevehoover
    Great job, @mayank-kabra2001 with this blog post on Verilog vs. TLV: https://mayank-kabra2001.github.io/My-BlogPost/
    mayank-kabra2001
    @mayank-kabra2001
    Thanks a lot , Sir.
    develone
    @develone
    @stevehoover This is the cnd I am using to synthesise the array from Makerchip "yosys -l simple.log -p 'synth_ice40 -blif top.blif -json top.json' top.sv pseudo_rand.sv". See "https://github.com/develone/sandpiper_test/blob/master/array/simple.log".
    Steve Hoover
    @stevehoover
    @develone What's 'top.json'?
    develone
    @develone
    yosys creates the bilf and json files used by nextpnr to do the place and route. When it goes ok see https://github.com/develone/sandpiper_test/blob/master/test2/blinky.json
    Steve Hoover
    @stevehoover
    thx @develone
    develone
    @develone
    @Ákos-Hadnagy @stevehoover Testing makerchip app. Cloned the repo when doing pip install . "Could not find a version that satisfies the requirement native_web_app (from makerchip-app==0.1) (from versions: )
    No matching distribution found for native_web_app (from makerchip-app==0.1)"
    1 reply
    Steve Hoover
    @stevehoover
    @JayDigvijay RE: adding cache and IOs to WARP-V... this would be nice to have. We would need to clearly define the desired outcomes and the benefits this would provide to the open-source community. For example: demonstrating use of memories in TLV, extending the configurability benefits of WARP-V beyond the core to cache and I/O, etc. We should consider whether coding fresh in TLV vs. leveraging another environment offers more benefit. We have started down the path of integrating WARP-V with other SystemVerilog SoC infrastructure, where we have made the most progress with OpenPiton. And before we get ahead of ourselves, you should identify a smaller starter project/example to put together for your own ramp-up and so I can understand what you are capable of.
    1 reply
    @JayDigvijay For GSoC, please favor communication here vs. Slack as this is a public forum. Thx.
    Digvijay Singh
    @JayDigvijay
    @stevehoover I have been trying to implement a Cache in TLV, as discussed. However, I am facing some difficulties with the syntax, especially the M4 macros. Is there any documentation available for these macros? I have searched extensively but haven't had any success. Would be grateful if someone could help me understand those macros. Thanks.
    2 replies
    Steve Hoover
    @stevehoover
    @ahadnagy can help you as well, @JayDigvijay . I've decided to open the TL-Verilog User's Slack channel to the public, so it is appropriate also for GSoC conversation: https://join.slack.com/t/tl-verilog-users/shared_invite/zt-4fatipnr-dmDgkbzrCe0ZRLOOVm89gA
    develone
    @develone
    @stevehoover & @ahadnagy I have been upgrading my FPGA Tools autofpga, yosys, nextpnr, All of tools (autofpga, icestorm, nextpnr, yosys, zipcpu, and verilator) are running on a RPi4. This is the debugger in a loop running in a simulation https://github.com/develone/catzip/blob/tst/doc/dbg-loop.pdf. This setting a break point https://github.com/develone/catzip/blob/tst/doc/break.pdf loading the program and running the debugger. The simulator provides Verilator tracing https://github.com/develone/catzip/blob/tst/doc/sim-bkram.pdf. Some of the hardware tests https://github.com/develone/catzip/blob/tst/doc/hardware-testing.pdf. Let me know if any of this is of interest. Has anyone here used any of these tools?
    Steve Hoover
    @stevehoover
    @develone Cool. Other than Verilator and yosys, I haven't used these.
    develone
    @develone
    @stevehoover & @ahadnagy https://github.com/develone/catzip/tree/addr23 this is the current branch. The toplevel Makefile should create the simiulator and a bit file that runs on ice40 HX8K See the commit log https://github.com/develone/catzip/tree/addr23. Do you think this could be integrated into makerchip-app? It would be great to compare warp-v with zipcpu.
    4 replies