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    Nic30
    @Nic30
    @hgomersall it is avaliable, just without hugepages and PCI-e, which is painfull...
    There is an extra library which allocates normal pages instead of hugepages as it is in default DPDK.
    Henry Gomersall
    @hgomersall
    Ah, this is very interesting
    it's even potentially worth money
    Nic30
    @Nic30
    The rte_mempools is overriden to work like this.
    Henry Gomersall
    @hgomersall
    Is it a NIC?
    Nic30
    @Nic30
    It is standalone DMA used in smartNICs
    Henry Gomersall
    @hgomersall
    smartNICs?
    Nic30
    @Nic30
    nic with fpga where user can put it's design/ p4 pipeline/ OvS accelerator and this kind of things
    Henry Gomersall
    @hgomersall
    (fast data from ARM on zynq w/ Linux is something I've been working towards for awhile, and the solution is still a WIP)
    So you have a DMA that pushes data to a fabric NIC?
    Does it work out-of-the-box so to speak?
    Nic30
    @Nic30
    It is designed to work so, however nothig related to DPDK is out of the box. The HW is ipcore with you can just drop in the design in Vivado quartus, that is not a problem, but the dpdk drivers.... it requre some knowledge of DPDK...
    Henry Gomersall
    @hgomersall
    yeah, I looked into DPDK but it's not exactly easy to access
    I didn't put too much effort in because I didn't have the NIC hardware that worked with it
    (unless you're aware ot DPDK drivers for the hard NIC on the zynq?)
    Regarding the original question, we're very interested but I think have something that works for the moment
    Nic30
    @Nic30
    I saw some experimets. I never saw anything which was usable.
    OK I was thinking the same, just checking what others thik.
    Henry Gomersall
    @hgomersall
    @alexforencich corundum looks nice too, but not immediately useful to us using zynq 7000
    (how much is ultrascale specific?)
    Nic30
    @Nic30
    I do not even see if it uses AXI4 or ACE
    Henry Gomersall
    @hgomersall
    Is ACE needed?
    Nic30
    @Nic30
    As it asserts cache coherency on HW level, such a DMA can perform much better.
    Henry Gomersall
    @hgomersall
    isn't that done with the ACP port?
    which presents as AXI4
    Nic30
    @Nic30
    it is but it is not prefered solution and ACP port is slow and can polute CPU chache
    Henry Gomersall
    @hgomersall
    that's crap - do you have any docs on that?
    Nic30
    @Nic30
    ACP is just AXI4 which is connected to snoop controller and the ACE is an AXI4 with an extra wires for cache management in whole memory subsystem
    Henry Gomersall
    @hgomersall
    Actually, we did some tests and found ACP wasn't much slower than HP
    Nic30
    @Nic30
    Which doc would you like? There is doc for SoC, and ACE
    Henry Gomersall
    @hgomersall
    anyway, that suggests ACE is hardware specific, so I imagine ultrascale?
    For ACP breaking things
    (the docs I mean)
    Nic30
    @Nic30
    2-acp-rw.png
    Henry Gomersall
    @hgomersall
    fair!
    is the top line using the HP bus?
    Nic30
    @Nic30
    2-HPx-rw.png
    No it is on second graph
    the top is write
    Henry Gomersall
    @hgomersall
    write which way? from CPU to FPGA?
    Nic30
    @Nic30
    from FPGA to DDR/CPU
    Henry Gomersall
    @hgomersall
    the second graph is read and write HP?
    ah, ok
    so it's slow to DMA to DDR with the ACP
    Nic30
    @Nic30
    also I think we really spaming this group, let's switch to a differen channel
    Henry Gomersall
    @hgomersall
    but HP is the same
    ok, struggling with gitter...
    Nic30
    @Nic30
    it is nearly same, but not same, also things get's mutch worse if CPU is working
    Alex Forencich
    @alexforencich
    Corundum is designed to run as a PCIe NIC for installing in a datacenter grade server, not currently for SoCs. But I have been considering what it would take to support an SoC such as the Zynq. Right now, the limitation is just the interface - it currently only supports the ultrascale series PCIe interface. Nothing else in the design is specific to any FPGA family.