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Repo info
Activity
    Martin
    @hackfin
    Partial assignments of signals?
    Henry Gomersall
    @hgomersall
    The github site seems to be workbooks, but I assume there is some backing library?
    Is that in with the examples?
    Josy Boelen
    @josyb

    We probably still need to fork then!

    @hgomersall I sent a message to our BDFL asking him to assign merging rights to other active MyHDL users/supporters.

    Josy Boelen
    @josyb

    That's entirely your problem. I am not soliciting. You're trolling.

    @hackfin Saying that I am trolling is an insult: I am profoundly concerned about the MyHDL community.
    From my side I apologize for using the word soliciting.

    Martin
    @hackfin
    @hgomersall : that would be the myirl kernel which is preinstalled in the container
    Henry Gomersall
    @hgomersall
    @hackfin is that on github too?
    Martin
    @hackfin
    No, but could be migrated to gitlab
    Henry Gomersall
    @hgomersall
    where is it at the moment?
    Martin
    @hackfin
    on a local gitlab setup
    It's not usable at this moment, I'm afraid. Too many dependencies to resolve.
    So for now you'll have to scavenge sources from the container
    Henry Gomersall
    @hgomersall
    :)
    polgarci
    @polgarci
    Hi, I have a question about MyHDL. Is it possible to quickly run the design made in MyHDL on a FPGA?
    In case you don't understand the question, I want to quickly run the design on the FPGA to check its performance. Then I would need some tool that is compatible with MyHDL that has the layout of the FPGA pins.
    Josy Boelen
    @josyb
    @hgomersall Our BDFL has given me admin rights to the MyHDL repositories. Will you assist in weeding through the open pullrequests?
    Henry Gomersall
    @hgomersall
    @josyb good work!
    Yes of course
    @polgarci What FPGA? Typically MyHDL is used as the first stage in the workflow
    Our workflow looks like this:
    MyHDL + MyHDL tests => Converted code + converted tests (in Vivado) => then one of (a) when the interfaces change, manual construction of Vivado project and converted HDL integration or (b) automatic creation and synthesis etc of a project using tcl scripts
    Henry Gomersall
    @hgomersall
    If the interface changes, we tweak the scripts by manually using the normal vivado workflow then exporting the changed tcl scripts
    Josy Boelen
    @josyb
    @polgarci A quick route to FPGA might be going with Yosys: https://www.yosyshq.com/open-source
    Henry Gomersall
    @hgomersall
    @josyb have you done any triage on the pull requests?
    It's not clear to me about the state of the PRs, nor what other issues need fixing imminently. Is the python 3.9 issue solved?
    3.9 issue looks fixed
    Henry Gomersall
    @hgomersall
    I recall there is an issue with _nameValid for enums. I have a fix in place in by branch which optionally puts names into a namespace, as in the case of enums. I can raise a PR for this easily enough once we get rolling with the PRs
    (I need your PR to be merged asap!)
    @josyb
    (it's better than a second level of name mangling as it's currently done)
    There seems to be no equivalent for Verilog, checking valid names. Am I missing something?
    Josy Boelen
    @josyb

    3.9 issue looks fixed

    @jck last action ...

    (I need your PR to be merged asap!)

    I still need to find out how to merge :( - not enough free time: we are moving house come March 30th, and you can appreciate the pressure :)

    Josy Boelen
    @josyb

    There seems to be no equivalent for Verilog, checking valid names. Am I missing something?

    The name checking was originated by @nicopy who did not do Verilog stuff.

    Henry Gomersall
    @hgomersall
    Ah ok. I can add that then
    I suggest we merge what's available and then do that
    If you can do that one PR, I can do some more stuff
    (click on the merge button within the PR!)
    Josy Boelen
    @josyb
    OK
    I suppose I have to a squash and merge
    PR#336 you mean
    That was easy :)
    Henry Gomersall
    @hgomersall
    Whoop! we're off again!
    Josy Boelen
    @josyb
    @hgomersall I noticed that Travis-CI doesn't run for the latest PRs. Can you help with this?
    Josy Boelen
    @josyb
    @hgomersall Dave Keeshan helped us get Github Actions running, replacing the Travis-CI .
    Could you take a look at some of the other PRs?
    Matti Picus
    @mattip
    Hi. I used MyHDL over a decade ago to model some image processing kernels. The hint to use PyPy for simulation performance led me to spend way too much time contributing to PyPy. The performance documentation page https://www.myhdl.org/docs/performance.html was my gateway. I would like to add the benchmarks there to https://speed.pypy.org but have forgotten how to run them. Are there clear instructions somewhere how to reproduce this data?
    Josy Boelen
    @josyb
    @mattip I suppose you just run some of the .sh scripts in myhdl\scripts\benchmark
    BUT: the source files need to be updated to MyHDL version 0.11
    Josy Boelen
    @josyb
    @hgomersall Can you spare a little time to look into some PRs?
    Henry Gomersall
    @hgomersall
    Sure, are there some in particular?
    Josy Boelen
    @josyb
    No, choose one or more