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    Henry Gomersall
    @hgomersall
    It seems undriven signals are assigned as None
    We'll raise a fix PR
    @josyb did you ever get your signal naming stuff merged?
    Henry Gomersall
    @hgomersall
    Has anyone had the tests working with GHDL on ubuntu recently?
    Josy Boelen
    @josyb

    @josyb did you ever get your signal naming stuff merged?

    Nope ...

    Thomas Hornschuh
    @ThomasHornschuh

    Has anyone had the tests working with GHDL on ubuntu recently?

    @hgomersall Can you specify "recently"? :-) I did run the tests during my PR regarding intbv initialization. It was last summer. The PR did also contain a few fixes for ghdl test issues when I remember right.

    Henry Gomersall
    @hgomersall
    uhm, Ubuntu 20.04
    Thomas Hornschuh
    @ThomasHornschuh
    I had also some discussion with @hackfin on the topic here...
    Henry Gomersall
    @hgomersall
    yeah, it seems a bit broken on my fairly old tree
    old being ~April 2020
    Thomas Hornschuh
    @ThomasHornschuh
    This was the pr myhdl/myhdl#345
    Some of the tests also crashed the ghdl version I was using at that time. Updating to the latest ghdl solved it.
    Henry Gomersall
    @hgomersall
    Yup, I probably need that
    I was waiting on myhdl/myhdl#336 being merged first, which makes our interface names sane
    I need to raise a PR on the fixes we've done to the concat signal when a sub-signal is not driven
    Thomas Hornschuh
    @ThomasHornschuh

    uhm, Ubuntu 20.04

    OK. I think I also run the myhdl tests on Ubuntu 20.04 / WSL (WIndows Service for Linux). Need to check...
    My Linux VMs are mostly 18.04 or 16.04 (follow the Vivado support...)

    Henry Gomersall
    @hgomersall
    I'll try with the fix. Thanks!
    develone
    @develone
    Hello All I have several Verilog modules. Is there a way to use these with a MyHDL design without rewriting them?
    Henry Gomersall
    @hgomersall
    @develone yes, absolutely. It would require wrapping the interface though to expose it to MyHDL.
    A more complicated than you probably need is done with Ovenbird: https://github.com/hgomersall/Ovenbird/blob/master/ovenbird/vivado_ip.py
    That example wraps Vivado IP-XACT IP
    But a similar approach could be used for general Verilog modules
    Nicolas Pinault
    @NicoPy
    It works for conversion but not for simulation. Right ?
    Henry Gomersall
    @hgomersall
    To be clear, you lose the simulation
    *snap.
    The simulation side we've found to be less problematic than might appear at first
    Because you don't actually need to implement it in hardware, you can cheat and implement it in non-convertible python
    That is perversely beneficial for IP blocks, because you end up really understanding the IP block, without wasting lots of time on the low level HDL.
    Martin
    @hackfin

    To be clear, you lose the simulation

    Why? Co-Simulation objects work fine..

    Henry Gomersall
    @hgomersall
    Oh, you're right. I had in mind encrypted IP, which is a bit harder
    Martin
    @hackfin

    Has anyone had the tests working with GHDL on ubuntu recently?

    yes, I've got them in the CI. Running into stdout/stderr confusion?

    develone
    @develone
    @hgomersall Thanks for information on using a wrapper Ovenbird. I will take a look.
    Henry Gomersall
    @hgomersall
    Ovenbird might be a bit fiddly to use for the simple use case, but the approach is more generally useful.
    develone
    @develone
    @hgomersall I added "https://github.com/develone/Ovenbird/blob/master/examples/echotest/simple_wrapper.py". The Verilog code that I want to use with MyHDL is "https://github.com/develone/Ovenbird/blob/master/examples/echotest/echotest.v". I am trying to understand the mapping. Should the MyHDL module be ECHOTEST or echotest? The Verilog signals are (i_clk, i_uart_rx, & o_uart_tx). The MyHDL signals should be (clock, RX, TX). Is this the correct way to create the wrapper.
    Henry Gomersall
    @hgomersall
    @develone hey wow, that's brave!
    If you want to pursue this, and there is definitely potential value in doing so, this first thing I think is to create an equivalent of VivadoIP (something like VerilogIP)
    That's where the actual mapping happens. The dsp48e1/simple_wrapper.py is really just an example of how to use a lower level module and is not necessary. The actual interesting usage is in dsp48e1.py.
    Henry Gomersall
    @hgomersall
    There are two levels to the problem - the factory class (called VivadoDSPMacro), which is instantiated here: https://github.com/develone/Ovenbird/blob/b626798e79477d18f99554c3ecedde0302eaa347/examples/dsp48e1/dsp48e1.py#L164
    The factory object is then used to create specific instances of the implementation
    E.g. line 341/342 of that file
    DSP48E1 is the MyHDL version of the IP block
    That can be used as normal in any MyHDL simulation, and converted as needed
    You'll notice that line 341 sets the Verilog code attribute using get_verilog_instance() on the factory.
    Henry Gomersall
    @hgomersall
    Every time that's called, a new string-like object is created. For the purposes of MyHDL, it's just a string containing some Verilog. However, it also contains the underlying IP object (which in your case would be a VerilogIP object representing your Verilog modules)
    You can then traverse your hierarchy and extract those underlying IP objects. An example of this being done is here, which uses a recursive look up function
    (that function takes a block, and returns a list of all the IP factory instances that are used. The set call then prunes out replications).
    There is some tooling interaction needed at this point, in telling the tool which additional IP blocks (which in your case would be additional Verilog files) are needed. Those come from the (to be written) VerilogIP objects you just looked up.
    Henry Gomersall
    @hgomersall
    Anyway, that's the design.
    You have a simpler implementation in that since you have the Verilog, if you're using cosimulation you don't need to create a specific implementation in MyHDL
    This might all be much easier with the built in MyHDL cosimulation machinery, but it's not immediately obvious how to me for the general case and I have limited experience of using that.