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    Henry Gomersall
    @hgomersall
    I suspect as much as anything, it's us doing things like presenting at conferences
    @cfelton has done a bit of that, but we're not so great overall
    we're all busy!
    Martin
    @hackfin
    I guess the RISC-V hype will be over at some point, too.
    Henry Gomersall
    @hgomersall
    risc-V is pretty awesome
    (IMHO)
    Martin
    @hackfin
    But technically just an improved MIPS/DLC
    The major change is the political movement behind it, I guess
    Henry Gomersall
    @hgomersall
    whatever, I'm ok with that
    Exactly!
    Thomas Hornschuh
    @ThomasHornschuh
    The interesting question is on which point of the Hype-curve RISC-V actually is. I think in the long run China will become the most important RISC-V adopter because the Chinese/US trade war cuts access to technlogies like ARM
    Martin
    @hackfin
    They've already had Loongson for a while..
    Henry Gomersall
    @hgomersall
    the micro magic risc-v stuff is an example of what we should expect more of
    (although, granted, that's mostly a press release as far as I'm concerned)
    Martin
    @hackfin
    that was a 64 bit workstation edition, right?
    Henry Gomersall
    @hgomersall
    the 5GHz core
    11,000 coremarks at 200mW
    Martin
    @hackfin
    Darn!
    Thomas Hornschuh
    @ThomasHornschuh

    The major change is the political movement behind it, I guess

    Indeed, it is all about having an open ISA, which did not exist before in this way. The other big selling point is the modula concept of the ISA. RV32I is so simple that everybody with average HDL skills can design a CPU executing it. And you can just use the out-of-the-box GCC to compile code for it

    Martin
    @hackfin
    But we had that for more than a decade with MIPS already.
    Just if there wasn't that license chaos.
    Henry Gomersall
    @hgomersall

    And you can just use the out-of-the-box GCC to compile code for it

    Unless you're writing rust ;)

    Thomas Hornschuh
    @ThomasHornschuh
    The trick was marketing the ISA separate from the implementation. This was not done before with e.g. OpenRISC, SPARC, etc.
    Henry Gomersall
    @hgomersall
    Arguably, that's what ARM have been doing all along
    perhaps the lesson could have been learnt
    Thomas Hornschuh
    @ThomasHornschuh
    Yes, but they sell the right to make you own Architecture based for a much higher price than licensing their RTL. So there are a very few companies with an architecture license.
    Henry Gomersall
    @hgomersall
    I think probably the big change was ISA verification
    (which ARM have?)
    which comes with separating the ISA conceptually
    Martin
    @hackfin
    That was already feasible with the MIPS ISA, too
    Thomas Hornschuh
    @ThomasHornschuh
    Basically RISC-V verification suite is a rework of old MIPS stuff.
    Martin
    @hackfin
    Just on the debugger side, risc-v has divergence again.
    (in circuit emulation)
    Thomas Hornschuh
    @ThomasHornschuh
    I think the extensions also prove a threat on RISC-V success. There are everlapping extensions (e.g B (bitmanip) and P (integer SIMD). All the SoftCore people comlain that mainline Linux requires RV64G

    Just on the debugger side, risc-v has divergence again.

    RISC-V debug spec is also quite incrompensible to read and there is no good reference debug server implemtation - it is just a patched OpenOCD.

    But we are far off-topic from MyHDL :-)
    Martin
    @hackfin
    @hgomersall, to get back to your rust insights concerning python wrappers: did you to any in depth testing on ownerships? like, simple thing you create an object in python and destroy it from the rust side..that sort of stuff.
    Henry Gomersall
    @hgomersall
    no, but that's ostensibly taken care of by pyO3
    destroying in python seems fine - the usual drop semantics happen
    Martin
    @hackfin
    That's what the boost libs claim, too...
    Henry Gomersall
    @hgomersall
    except that rust has a much better ownership model
    Martin
    @hackfin
    That's why I'd consider rust.
    Henry Gomersall
    @hgomersall
    the other way round, you need to interact with the python run time to do stuff I believe
    Martin
    @hackfin
    So as I understood, it can transfer ownership to another layer
    I don't want like a proxy telling me: The object you just try to access was deleted.
    Henry Gomersall
    @hgomersall
    well there is no proxy
    it's all statically determined
    to take ownership, you need to take it explicitly
    Henry Gomersall
    @hgomersall
    The statically enforced ownership model is The Big Conceptual Change with rust.
    Josy Boelen
    @josyb

    But we are far off-topic from MyHDL :-)

    Indeed.