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    Josy Boelen
    @josyb
    for Lattice
    jdavidberger
    @jdavidberger
    it does; so long as I only have one fifo module in the generated module. For some reason, when it has more than one it rejects it
    the usercode stuff seemed to miss the ability to reference the unique block name; so it'd break. I modified UserVerilogInstance to: https://gist.github.com/jdavidberger/bdc70abdac5b9378c341d328125186a2
    which works and allows multiple modules to be instantiated (there is a change somewhere else to to add block to the object here)
    Josy Boelen
    @josyb
    There should be no issue with inferring multiple RAM blocks. In one of my projects I have dozens.
    Your suggested enhancement for UserVerilogInstance may have its merits, but I feel we should look at the base problem. Perhaps we can take a look at your code and what it converts to?
    I never use VHDL (in my case) modules as it severely hampers simulation.
    jdavidberger
    @jdavidberger
    I'll see if I can get a minimal example. My read on it was that lattice was just being annoying; yosys had given me similar issues already
    Josy Boelen
    @josyb
    You mean that the generated Verilog code is badly digested by both Yosys and Lattice's tool?
    jdavidberger
    @jdavidberger
    yosys didn't map to ram when I just had one FIFO block; lattice did
    neither tool liked multiple FIFOs
    possibly it was a bad design in some way but simulations looked like what I expected
    Josy Boelen
    @josyb
    But if you instantiate UserVerilogCode modules, it will pass?
    jdavidberger
    @jdavidberger
    yes
    Josy Boelen
    @josyb
    then we must look at your MyHDL code and what MyHDL makes from it.
    jdavidberger
    @jdavidberger
    might need to wait til tomorrow; I redid the design later to optimize BRAM usage so it just needed one fifo
    but I can make some minimal test case
    Josy Boelen
    @josyb

    possibly it was a bad design in some way but simulations looked like what I expected

    Yes, unfortunately what simulates doesn't always synthesize

    jdavidberger
    @jdavidberger
    Hrm. I maybe should have ran the sythened design. It did synthesize, just by blowing a bunch of LUTs
    Nicolas Pinault
    @NicoPy

    @NicoPy I promote not-driven but read Signals to constant forcing the initial value.
    This works fine for VHDL (and is in fact what you want...)

    @josyb Interresting. Thanks.

    @jdavidberger

    So I'm having issues with lattice doing proper inference on BRAM.

    Which toolchain do you use with Lattice IDE ?

    Native Diamond toolchain or Symplify Pro toolchain ?
    Josy Boelen
    @josyb

    Hrm. I maybe should have ran the sythened design. It did synthesize, just by blowing a bunch of LUTs

    Looks to me that your RAM has a reset signal?

    jdavidberger
    @jdavidberger
    there is some reset stuff I'll have to look through to make sure it's not completely dumb; but it was mostly because it was synthesizing ram out of LUTs
    @NicoPy Synplify pro
    jdavidberger
    @jdavidberger
    Hrm; minimal replication generates to bram so it must have been some other criteria on din/dout
    jdavidberger
    @jdavidberger
    i'll tweak it later this week to see if i can find what exactly it was. I'd still like to PR that code; i think it is helpful for veriloginstances in general -- although I think thats still a sort of secret feature?
    namely it adds constant parameters and unique names
    Henry Gomersall
    @hgomersall
    Re constant assignments... This works too:
    def assignment(data_out2):
    
        const_val = intbv(0xFFFFFFFF80)[64:]
        keep = Signal(True)
        keep.driven = True
    
        drive_signal = ConcatSignal(keep, const_val)
    
        @always_comb
        def do_it():
            data_out2.next = drive_signal[64:]
    
        return do_it
    It's interesting that ConcatSignal works properly with intbvs
    Nicolas Pinault
    @NicoPy
    It works but it's very complex.
    Henry Gomersall
    @hgomersall
    not really in the converted code
    it actually works well in my particular use case
    because I generally have a concat signal
    the problem occurs when I only have a single signal or a single const
    in that case, the above strategy works for both
    Really, concat signal should take a single argument
    I'm not sure why it doesn't
    Should allow a single argument
    Nicolas Pinault
    @NicoPy
    not really in the converted code
    I "don't care" of converted code.
    I write source code which, in your example, is really verbose.
    Henry Gomersall
    @hgomersall
    Really?
    It uses two extra lines
    one of which is replaced by a toVHDL.initial_values = True ;)
    Nicolas Pinault
    @NicoPy
    Four lines while we should be able to use none.
    Henry Gomersall
    @hgomersall
    Oh, I agree with that
    we're just debating the various levels of hackery
    Nicolas Pinault
    @NicoPy
    Right. No hack is perfect, by nature. But the more verbose, the least readable, from my point of view.
    Henry Gomersall
    @hgomersall
    I put it there as a potentially useful contribution. It fits my use case well in this situation, but probably not others.
    Nicolas Pinault
    @NicoPy
    And you did the right thing :)