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    stnolting commented #218
SaabFAN
@SaabFAN

Has anyone built an external Wishbone to Avalon-Bridge for the NeoRV32?
My FPGA (Intel Max 10) is connected to a 8 MB SDRAM and also contains some flash memory available for User-Data.
I've found an SDRAM-Controller with a Wishbone interface, but the User Flash can only be accessed by an IP from Intel, which has the Avalon Interface.
So now I've got 2 memory controllers that use 2 different interfaces.

My idea was to use the Avalon-Bridge contained in the Avalon-Enabled neorv32 example with some additional logic that detects whether RAM or ROM are addressed and then selects the right data-path.

1 reply
Stephan Nolting
@stnolting
There is an example setup in setups/quartus that provides a simple Wishbone <=> AvalonMM bridge
GitHub user @emb4fun recently implemented a bridge for a generic SDRAM controller by @nullobject
Michael Fischer
@emb4fun_gitlab
@SaabFAN which board you are using, e.g. the DE10-Lite? Here I have a working example based on Wishbone to Avalon-Bridge for a DE0-nano board. But I have the DE10-Lite too.
7 replies
Michael Fischer
@emb4fun_gitlab

Hello everyone, I'm currently working on a neorv32-example project that uses Intel boards as targets. Furthermore, the focus is on the use of a debugger for software development. Here I am currently using the "SEGGER Embedded Studio for RISC-V". For the beginning I use the DE0-Nano board. That is why there will be the first examples of this. Examples are planned that show how to connect SDRAM native via the Wishbone bus, or via a Wishbone to Avalon Bride for Qsys.

The GitHub project is available here:
https://github.com/emb4fun/neorv32-examples

And if you want to know what else I'm doing:
https://www.emb4fun.de

:o)

Stephan Nolting
@stnolting
@emb4fun_gitlab great work! 👍
Hipólito Guzmán-Miranda
@hipolitoguzman
Hi all, we are using the neorv32 in the icebreaker FPGA board and we are seeing some strange behavior... we cannot get a program into the FPGA using the bootloader if it's longer than 4k. The last thing the processor says is the "Awaiting neorv32_exe.bin...". Any ideas of what could be causing this? Programs smaller than 4k work fine
We are using minicom, in ASCII mode, with the UART at the default configuration (19200 baud, 8-N-1, no hardware control flow)
Stephan Nolting
@stnolting
What memory configuration do you use? Seems like MEM_INT_IMEM_EN is set to 4kB.
Sorry, wrong generic. I meant this one MEM_INT_IMEM_SIZE
Hipólito Guzmán-Miranda
@hipolitoguzman
Thanks @stnolting . I am currently using 32*1024 for MEM_INT_IMEM_SIZE. I am also using the same size for the data memory (MEM_INT_DMEM_SIZE)
Hipólito Guzmán-Miranda
@hipolitoguzman
Ok, it seems that the problem lies with minicom, I can upload programs bigger than 4k with cutecom and everything works as expected
Unai Martinez-Corral
@umarcor
@hipolitoguzman see stnolting/neorv32#215
So, yes, it seems that minicom is problematic, since two of you had that problem independently.
Hipólito Guzmán-Miranda
@hipolitoguzman
thanks @umarcor for the link. I am reading and it seems that minicom doesn't have a binary transfer mode by default, and probably the 'ascii' mode is messing up the exectutable (if it's bigger than 4k)
Unai Martinez-Corral
@umarcor
@hipolitoguzman it would be nice if you could comment that in the PR. So that instead of recommending an "arbitrary" tool, we explain why some do work but other fail.
1 reply
Stephan Nolting
@stnolting
@hipolitoguzman are you using the SPRAM-based IMEM/DMEM modules for your setup? These modules have fixed size of 64kB each, so you should set MEM_INT_IMEM_SIZE and MEM_INT_DMEM_SIZE also to 64kB to utilize all of the available memory.
Hipólito Guzmán-Miranda
@hipolitoguzman

@hipolitoguzman are you using the SPRAM-based IMEM/DMEM modules for your setup? These modules have fixed size of 64kB each, so you should set MEM_INT_IMEM_SIZE and MEM_INT_DMEM_SIZE also to 64kB to utilize all of the available memory.

Yes, I am using the SPRAM blocks. I tried using a process that would get synthesized into the normal brams for the instruction memory, and when that didn't work (actually sythesis and P&R works for up to 9kB of IMEM, but of course the program got corrupted by minicom), I went back to the SPRAM blocks

Andreas Wenzel
@AWenzel83
I just tried to use the TWI interface of the neorv32 on the Nexys 4 DDR. When I use the TWI-Example to scan the bus, it fiends devices at every single Address. I can confirm, that the bus is low at any time (what looks like an ACK to the processor), which is obviously totally wrong, although there are pull-ups on the board. There should be a single ADT7420 temperature sensor (Configured to Address 0x4B). Do I need to do anything special, except for enabling the corresponding module and connecting the two pins? Or do I miss something?
Andreas Wenzel
@AWenzel83
Ok, I think I know whats wrong. I'm using the processor in a block design and generate a wrapper, which I use in a higher level hierarchical design. I just found the warning "converting tricell instance ... to logic" in the error log. It seems that Vivado cannot handle internal tristate signals. I just looked at the AXI-I2C Block, and they are using single Input and Output signals together with an input enable to move the tristate-logic to the top level.
Stephan Nolting
@stnolting
I know this problem with Vivado and the tri-state drivers...
"Set the synthesis option "global" when generating the block design to maintain the internal TWI tri-state drivers."
This is what worked for me (using some older Vivado version from 2020)
Andreas Wenzel
@AWenzel83
Thank you! Great, now that you mention it, I saw this note before, but couldn't remember, when I ran into the problem yesterday. I'm using Vivado 2020.1, too. Everything after that just grew exponentially...
2 replies
Hipólito Guzmán-Miranda
@hipolitoguzman
Hi @stnolting and @umarcor , I can happily say that today we have had our first lab lesson with the neorv32 and the icebreaker boards, and everything has been really smooth with the students. Actually, it has gone better than when we were using EDK & Microblaze, I see that they have more interest and curiosity: being able to look at the code, and the fact that everything is really well documented really helps!
Michael Fischer
@emb4fun_gitlab
A step by step tutorial for creating a NEORV32 system on a DE0-Nano is now available under:
https://www.emb4fun.de/riscv/neorv32/index.html
2 replies
Unai Martinez-Corral
@umarcor
@hipolitoguzman :tada: :heart:
Hipólito Guzmán-Miranda
@hipolitoguzman
Wow, I was going to make a PR with the iCEBreaker files but I have arrived two days late. Impressive! :D
Stephan Nolting
@stnolting
@hipolitoguzman great to hear!! :D
Irvise
@irvise:matrix.org
[m]
Hi! I did not introduce myself earlier. I somewhat recently found out about the project :) I have been looking for a VHDL microcontroller for some time and I finally found you.
I have a ULX3S and I hope to build it there (I know there is some basic support, it seems SDRAM was added recently). I already tried getting a "bigger" design (more IO, more functionallity) on the synthesised design but I did not get that far. I hope that in a few months I will be able to give it another take.
Stephan Nolting
@stnolting
@irvise:matrix.org welcome! :)
@zipotron is the one who is currently pushing the SDRAM support for the ULX3S board
I already tried getting a "bigger" design (more IO, more functionallity) on the synthesised design but I did not get that far
Do not hesitate to ask if you are encountering any problems during setup
Irvise
@irvise:matrix.org
[m]
For the time being I may do an Ada abstraction layer ala https://github.com/Irvise/Ada_SaxonSOC
What I found reaaaally nice is that you have the registers already documented. For the SaxonSoc I had to look into the autogenerated C header files and decrypt what the C example programs where doing...
Wouldn't you, by any chance, be capable of generating CMSIS-SVD hardware description files?
Stephan Nolting
@stnolting
I wasn't really aware of SVD until @emb4fun_gitlab pointed it out to me. I think it would be very handy for things like IDE integration (thinking about the on.chip debugger...).
CMSIS SVD is ARM tchnology. As far as I know, there isn't something similar in the RISC-V ecosystem (so far).
However, I found some SVD files for SiFive platforms like this https://github.com/riscv-rust/e310x/blob/master/e310x.svd
I don't know if this is exactly the CMSIS SVD format. But I think CMSIS SVD is open-source with a permissive license, so it should be no (legal) problem to setup such a file for the NEORV32. Actually, I would be really interested in that! ;)
Irvise
@irvise:matrix.org
[m]
CMSIS-SVD is an open specification, so anybody can use it. CMSIS refers to the Cortex cores, so for other platforms it is generally simply called SVD. SiFive does indeed have some .svd files for their cores.
That is how the Ada bb_runtimes (bare bones) were created for the SiFive cores. There are tools to create Rust bindings as well . And obviously C headers.
SiFive has a SVD generator from DTS files... Maybe this could be used: https://github.com/sifive/cmsis-svd-generator/
Irvise
@irvise:matrix.org
[m]
I thought that NeoRV32 already had something similar since you have a nice and thorough documentation on the Registers and peripherals.