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    Skip Hansen
    @skiphansen
    if you have a scope it would be worth while looking at the USB lines @ the keyboard ... if nothing else to see if they are wiggling...
    Did you power up the ports, etc?
    the hub reports connections status
    Martin Povišer
    @povik
    Looking at section 8.6.5 of the USB 1.1 spec it's clear that the host must distinguish between full-speed and low-speed devices, even if there are hubs inbetween
    Which is missing in the core, as there's no way to tell it it's going to talk to a low-speed device
    Skip Hansen
    @skiphansen
    his ulpi layer works at 2.0 speeds, I wonder how hard it would be to add a 1.1/2.0 speed switch.
    Martin Povišer
    @povik

    the hub reports connections status

    Right. I am reading the port states from the hub, and a USB flash drive can be enumerated when connected to the hub, so it seems full-speed devices work

    Skip Hansen
    @skiphansen
    once you are at 2.0 speeds you definitely don't won't need the core to deal with low speed signaling.
    ah! Great!
    "shift to warp speed number 1 !"
    Martin Povišer
    @povik

    once you are at 2.0 speeds you definitely don't won't need the core to deal with low speed signaling.

    That may be the case, but the core from ultraembedded is 1.1 only, it won't reach 2.0 speeds

    Skip Hansen
    @skiphansen
    I guess there's always PS2 keyboards...
    Martin Povišer
    @povik
    :)
    I am not yet discouraged
    Skip Hansen
    @skiphansen
    good!
    I don't think it would be super difficult to make it dual speed. The ulpi works already. Run at 1.1 speed, enumerate the hub, switch to 2.0 speeds, done. No need to deal with dynamic switch between speeds or anything fancy. Once you're at 2.0 speeds the hub does all of the work for converting transactions to low speed and full speed, the upstream (host) just needs to deal with "high speed".
    Martin Povišer
    @povik
    The hub taking care of lower speeds is indeed convenient. The question is then how much work is it to get an USB 2.0 host when you have an 1.1 one
    Do you know the scope of changes in USB 2.0 compared to 1.1, beyond the obvious speed changes?
    Skip Hansen
    @skiphansen
    AFAIK The bit format on the wire which the PHY takes are of for you, and software differences.
    buffer sizes are bigger, etc.
    the start of frame (sof) timing is different and there are micoframes too... sort of forgot about that.
    I've search a lot and didn't find any free 2.0 device side cores. Ultraembedded's 1.1 core is the best one I found.
    Martin Povišer
    @povik
    You mean host-side cores?
    Skip Hansen
    @skiphansen
    yea, that's what I meant. There are lots of device side cores.
    where lots := more than one.
    DrWhax
    @DrWhax
    I'm going to leave a bunch of PanoLogic G2's with the LX150 at the Techinc Amsterdam, i'm moving and I just cannot move this stuff with me.
    So if you ever want to have one, drop by, when this whole pandemic is over I guess
    chaseadam
    @chaseadam:matrix.org
    [m]
    anyone seen the inside of an XD3? https://www.ebay.com/itm/133646988912
    Tom Verbeure
    @tomverbeure
    I had never heard about ncomputing before, but here is one of their devices that's running on top of a Raspberry Pi platform. I assume that all their products use some kind of ARM based SOC instead of an FPGA.
    Cary Goltermann Sr
    @goltermc
    Hi, New here. Been playing with a Pano Logic G2 and a neorv32 (Risc v processor) had problems attempting to program the flash using a digilent clone. Opened the pano to find that the flash is not a m25p128 it is an ST 25P64. I was able to do a readback, using impact with the device set to M25P64. As others have said, I had to hold down the pano button. Interestingly , it seems that it only needs to be held down till all three leds come on. Then the readback worked just fine.
    Tom Verbeure
    @tomverbeure
    Is that "hold down the pano button" procedure described somewhere? If not, we should probably document that in the main repo. Feel free to issue a pull request with an updated README.md. I haven't touched my Panos in a while, but I'm slowly getting back into the USB game.
    Skip Hansen
    @skiphansen
    It's mentioned in this ticket: tomverbeure/panologic-g2#7 But no where else that I know of.
    @goltermc That flash is expected for a REV-C, the REV-B has the larger flash. https://github.com/skiphansen/pano_progfpga/blob/master/Series2.md#differences-between-series-2-revisions
    Cary Goltermann Sr
    @goltermc
    Just to be clear, I was not complaining just took a while to figure out, thought I'd pass info along. It appears the impact loads a spi core into the fpga which is used to program the spi flash. After that the device needs to be powered down and back up to reload the users design into the fpga. It also appears that the flash can be read by the users design. Probably useful for someone doing a processor in the pano. Anyone here done that? I'm trying to find out which pins are used to do this.
    Skip Hansen
    @skiphansen
    @goltermc Yes several projects read the unused portion of flash for code/data. For example there's enough free space on a Rev-B Pano for a Linux rootfs ... https://github.com/timvideos/litex-buildenv/wiki/HowTo-Linux-on-Pano-Logic-G2
    Tim Ansell
    @mithro
    povik: Charles from VexRISCV has done a USB2.0 Host for an FPGA compatible with Linux IIRC
    Skip Hansen
    @skiphansen
    @mithro That's exciting! Link ??
    Tim Ansell
    @mithro
    I actually don't have any links to it...
    Try him in the #SpinalHDL/VexRiscv channel?
    Tom Verbeure
    @tomverbeure
    I've chatted with Charles about it. It's an OHCI compatible host, but it uses raw IOs, not ULPI.
    I've been working on getting ULPI up and running this weekend. I want a device going, and then host. I'm doing it first on an Arrow DECA board (much easier to debug than a Pano), but the goal, of course, is to eventually have a drop-in design for the G2.
    Skip Hansen
    @skiphansen
    @tomverbeure Cool! Sounds like it's time for me to clear off some bench space.
    Cary Goltermann Sr
    @goltermc
    @skiphansen Thanks for pointing me to the litex build. That had the spi pins I was looking for. I was about to start tracing through the board. Since these signals run from the fpga to the spi flash (which are on the main and upper board ) it might be useful to identify them on the board to board connector.
    Oleg Stepanov
    @reostat
    Does anybody have any news on Ethernet working on Pano?
    Skip Hansen
    @skiphansen
    @goltermc Checkout https://github.com/tomverbeure/panologic-g2, the board to board connector has already been traced out.
    @reostat Ethernet is fully up and working the G2 under Linux, see: https://github.com/timvideos/litex-buildenv/wiki/HowTo-Linux-on-Pano-Logic-G2. https://github.com/skiphansen/panog2_usb_sniffer also has working Ethernet with LWIP.
    Skip Hansen
    @skiphansen
    @reostat also see https://github.com/skiphansen/panog2_linux for a prebuilt image (Rev B only).
    bitmapper
    @bitmapper:lighthouse.cx
    [m]
    @tomverbeure: by the way, do you have any examples for the DECA?
    Tom Verbeure
    @tomverbeure
    @bitmapper:lighthouse.cx All the recent examples on my blog are done with the DECA. This one about Intel RAM updates. And this one about the JTAG UART. I don't have anything related to USB on the DECA yet. That's work in progress.