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    David Kuder
    @dkgrizzly
    I haven't sent the boards out, or even written the firmware for the greenpak that switches the CS line between the flash & psram, mostly because I have had some trouble sourcing the psram chips when I worked on that part last month.
    the idea is to attach a greenpak to one of the I2C busses, and use it to switch between the flash and psram, then trigger the fpga to reload from the psram after.
    since the spartan3 doesn't support multiboot.
    David Kuder
    @dkgrizzly
    I'll have to see if my roommate will let me steal a couple of his greenpaks and dig around for an spi psram, then I can breadboard it up and check my firmware is sound.
    Tom Verbeure
    @tomverbeure
    What's the greenpak?
    David Kuder
    @dkgrizzly
    yeah, its kinda partway between a pld and a mcu. the part I'm looking at using is an i2c expander & some small LUTs. so CS from the FPGA goes into the greenpak, depending on the state of one of the virtual I2C expander pins it chooses which chip gets the CS pulled low, and then theres a oneshot that blips the FPGA's reset line when the virtual pin goes high. plus 6 outputs for status LEDs or whatever.
    Gigabit Ethernet, 256MB NAND flash, xc7z010clg400, 1G DDR3, lots of pins going to connectors.
    and schematics, sample projects https://github.com/KarolNi/S9miner_sample I bought 2 for my pile of board that I haven't played with yet...
    fanoush
    @fanoush
    interesting, price US $14.99 shipping $182.70 UPS Worldwide Saver :-) have to look up what the word 'saver' means
    Skip Hansen
    @skiphansen
    yikes! I suspect they are available elsewhere with better shipping like aliexpress...
    fanoush
    @fanoush
    the NiteFury a.k.a. Acorn CLE-215+ is interesting cheap mining board see here or here, has some I/O too but mostly for learning/using pci-e bus
    Skip Hansen
    @skiphansen
    Few pins are available, but I bought one of those too...
    Schematics are also available for it.
    Tom Verbeure
    @tomverbeure
    I've had a NiteFury sitting in a box for months now. I was about to order that $11 Zynq board last night, but decided against it: too many unused boards already!
    Skip Hansen
    @skiphansen
    Most of the stuff that interests me ends up needing a monitor so the other boards pale when compared to either Pano pretty quickly, but ... well, that didn't stop me.
    Skip Hansen
    @skiphansen
    Yet another variation of the colorlight stuff, I have a couple of the older ones... haven't touched them yet (or the smart watches I bought to hack or ...)
    Zeljko Stevanovic
    @zsteva
    hi, any available information about pano board embeded in fujitsu zeroclient dz22-2?
    Skip Hansen
    @skiphansen
    It's basically a G2 as far as I know, probably the LX100 version. No one that I'm aware of has hacked one yet.
    Zeljko Stevanovic
    @zsteva
    in mine is lx150 and most chips is same. board have one unused 6 pin connector. i hop its jtag.
    Skip Hansen
    @skiphansen
    Be sure to let us know what you find. Good luck!
    Tom Verbeure
    @tomverbeure
    I have a Fujitsu one, but I haven't been able to open it up. I'll need Skip's remote update utility to work once I get to it.
    bzboi
    @bzboi

    in mine is lx150 and most chips is same. board have one unused 6 pin connector. i hop its jtag.

    can you share some photos? hopefully the bulk of the FPGA interfaces are the same pinout

    Zeljko Stevanovic
    @zsteva
    fanoush
    @fanoush
    what is pano-specific on xc3sprog spi loading bitstreams here ? Those work and other with same name included with xc3sprog give me error unknown jedec manufacturer ff
    I am asking because I need one for Acorn 215+ and this one gives me same error
    Skip Hansen
    @skiphansen
    The usual spi loading bitstream has a different default configuration for pins which causes the Pano power supply to the jtag vref to be turned off. That file has the correct default (sorry I don't remember the details). If you press and hold the Pano button while programming that keeps power on as well, but that's not particularly convenient.
    @zsteva well one difference from the G2 is it has an audio input. The G1 had an input, but it was dropped on the G2.
    Skip Hansen
    @skiphansen
    Well my new $15 Zynq 7010 toy boots anyway

    ```root@antMiner:~# cat /proc/cpuinfo
    processor : 0
    model name : ARMv7 Processor rev 0 (v7l)
    Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpd32
    CPU implementer : 0x41
    CPU architecture: 7
    CPU variant : 0x3
    CPU part : 0xc09
    CPU revision : 0

    processor : 1
    model name : ARMv7 Processor rev 0 (v7l)
    Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpd32
    CPU implementer : 0x41
    CPU architecture: 7
    CPU variant : 0x3
    CPU part : 0xc09
    CPU revision : 0

    Hardware : Xilinx Zynq Platform
    Revision : 0000
    Serial : 0000000000000000
    ```

    Tom Verbeure
    @tomverbeure
    So that's right out of the box? Just connecting JTAG?
    fanoush
    @fanoush
    that's perhaps console over serial? ordered one too, very cheap and interesting concept (for the price), if prjxray supports it it could be actually 'field programmable' - rebuild directly on the board
    fanoush
    @fanoush
    still not sure what is shared between ARM and FPGA , think I've read about some dual port SRAM block and couple of gpios for communication, wonder what peripherals on ARM side can be set on those pins, the picture doesn't explain much
    Skip Hansen
    @skiphansen
    Yea, right of of the box. Connected +12V and an Ethernet cable. SSH'ed in with root/admin. There's also a web page login root/root. There's a JTAG connector, not populated but the holes were masked so installing a connector should be easy. I haven't installed Vivado yet. Frankly I have zero idea what I'm going to do with it. Lots of easily accessible I/O, but no USB or video. There's a populated serial connector as well, but I haven't tried it yet.
    Skip Hansen
    @skiphansen
    This is the S9 antminer control board from ebay. The schematic from https://github.com/KarolNi/S9miner_sample.git seems to match the board perfectly.
    Martin PoviĊĦer
    @povik
    Hello pano hackers! I am happy to announce I have found a somewhat novel way to program my G2. I had issues with xc3sprog and my ft2232-based programmer (chain scan is ok but fpga programming fails with INSTRUCTION_CAPTURE is 0x3f). Now I tried IMPACT and a "xilinx virtual cable" server bridging to said ft2232 programmer, and it works! The bridging server in question is this one: https://github.com/wzab/xvcd-ff2232h
    Tom Verbeure
    @tomverbeure
    Good! I have added a "Programming" section to the repo README" https://github.com/tomverbeure/panologic-g2#programming.
    Skip Hansen
    @skiphansen
    Not that it's a good deal, but it's interesting that there are still unopened boxes of new Panos as shipped from Pano around: https://www.ebay.com/itm/124506064419?ul_noapp=true
    fanoush
    @fanoush
    so which one it is? g2 or something else?
    Skip Hansen
    @skiphansen
    good question, lazy seller, couldn't be bothered to take one out of the box for a picture. G1 apparently (by searching ebay for "PAC-102-NA" and looking at pictures from other sellers. This guy also has new in the box Panos with better pictures ... https://www.ebay.com/itm/LOT-OF-4-GENUINE-Pano-Logic-PANO-PAC-102-NA-Thin-Zero-Desktop-Client/184531877626?hash=item2af6f4fefa:g:7q4AAOSwh-dfrH08
    and a dual monitor adapter that I've never seen before.
    bzboi
    @bzboi

    Verilog question. I'm trying to port a Quartus design https://github.com/menloparkinnovation/menlo_gigatron/tree/master/release_09092018/menlo_gigatron_de10_nano over to the Pano. The design is for the most part a translation of the Gigatron schematic at https://cdn.hackaday.io/files/20781889094304/Schematics%202020-03-20.pdf with hooks to DE10-nano interfaces. I'd previously successfully implemented the same code in Vivado but am having issues in ISE 14.7. Looking at the code I'm specifically concerned about this section of code

      // we_n - Memory write enable when low.
      //
      // Conditioned by the OR gate U16A.
      //
      assign we_n = st_n | clock;

    It's not intended to be a gated clock, but it's essentially an AND of a clock and an active low store signal. ISE is throwing an error about the mixed clock and logic unless I use PIN clk_div_20/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; in the user constraint file.
    Phase 2.7 Design Feasibility Check WARNING:Place:1137 - This design is not guaranteed to be routable! This design contains a global buffer instance, <clk_div_20/clkout1_buf>, driving the net, <clock>, that is driving the following (first 30) non-clock load pins. < PIN: cpu/writeram_data<6>LogicTrst1.A4; > < PIN: cpu/writeram_data<2>LogicTrst1.A4; > < PIN: cpu/writeram_data<7>LogicTrst1.A4; > < PIN: cpu/writeram_data<3>LogicTrst1.A4; > < PIN: cpu/writeram_data<4>LogicTrst1.A4; > < PIN: cpu/writeram_data<5>LogicTrst1.A4; > < PIN: cpu/writeram_data<1>LogicTrst1.A3; > < PIN: cpu/ram_write1.A3; > This is not a recommended design practice in Spartan-6 due to limitations in the global routing that may cause excessive delay, skew or unroutable situations. It is recommended to only use a BUFG resource to drive clock loads. Please pay extra attention to the timing and routing of this path to ensure the design goals are met. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <clk_div_20/clkout1_buf.O> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.
    I was able to get to a bitstream but am seeing strange behavior. Any recommendations on how best to modify the assign statement? TIA!

    Thomas Cenova
    @tcenova_gitlab
    any chance you could generate a 2x clock and use that to generate a toggling ff at the rate of the 1x. that way it would not be using the clock signal directly. there may be other tricks to use the clock directly but it will have to pass through some block to get from the clock tree into the fabric. which may not be supported by that assign statement with a defined functionality in ise like it was in quartus.
    This message was deleted
    bzboi
    @bzboi

    any chance you could generate a 2x clock and use that to generate a toggling ff at the rate of the 1x. that way it would not be using the clock signal directly. there may be other tricks to use the clock directly but it will have to pass through some block to get from the clock tree into the fabric. which may not be supported by that assign statement with a defined functionality in ise like it was in quartus.

    That worked! Thanks!