```root@antMiner:~# cat /proc/cpuinfo
processor : 0
model name : ARMv7 Processor rev 0 (v7l)
Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x3
CPU part : 0xc09
CPU revision : 0
processor : 1
model name : ARMv7 Processor rev 0 (v7l)
Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x3
CPU part : 0xc09
CPU revision : 0
Hardware : Xilinx Zynq Platform
Revision : 0000
Serial : 0000000000000000
```
INSTRUCTION_CAPTURE is 0x3f). Now I tried IMPACT and a "xilinx virtual cable" server bridging to said ft2232 programmer, and it works! The bridging server in question is this one: https://github.com/wzab/xvcd-ff2232h
Verilog question. I'm trying to port a Quartus design https://github.com/menloparkinnovation/menlo_gigatron/tree/master/release_09092018/menlo_gigatron_de10_nano over to the Pano. The design is for the most part a translation of the Gigatron schematic at https://cdn.hackaday.io/files/20781889094304/Schematics%202020-03-20.pdf with hooks to DE10-nano interfaces. I'd previously successfully implemented the same code in Vivado but am having issues in ISE 14.7. Looking at the code I'm specifically concerned about this section of code
// we_n - Memory write enable when low.
//
// Conditioned by the OR gate U16A.
//
assign we_n = st_n | clock;It's not intended to be a gated clock, but it's essentially an AND of a clock and an active low store signal. ISE is throwing an error about the mixed clock and logic unless I use PIN clk_div_20/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; in the user constraint file.Phase 2.7 Design Feasibility Check
WARNING:Place:1137 - This design is not guaranteed to be routable! This design
contains a global buffer instance, <clk_div_20/clkout1_buf>, driving the net,
<clock>, that is driving the following (first 30) non-clock load pins.
< PIN: cpu/writeram_data<6>LogicTrst1.A4; >
< PIN: cpu/writeram_data<2>LogicTrst1.A4; >
< PIN: cpu/writeram_data<7>LogicTrst1.A4; >
< PIN: cpu/writeram_data<3>LogicTrst1.A4; >
< PIN: cpu/writeram_data<4>LogicTrst1.A4; >
< PIN: cpu/writeram_data<5>LogicTrst1.A4; >
< PIN: cpu/writeram_data<1>LogicTrst1.A3; >
< PIN: cpu/ram_write1.A3; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable
situations. It is recommended to only use a BUFG resource to drive clock
loads. Please pay extra attention to the timing and routing of this path to
ensure the design goals are met. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
<clk_div_20/clkout1_buf.O> allowing your design to continue. This constraint
disables all clock placer rules related to the specified COMP.PIN.
I was able to get to a bitstream but am seeing strange behavior. Any recommendations on how best to modify the assign statement? TIA!
any chance you could generate a 2x clock and use that to generate a toggling ff at the rate of the 1x. that way it would not be using the clock signal directly. there may be other tricks to use the clock directly but it will have to pass through some block to get from the clock tree into the fabric. which may not be supported by that assign statement with a defined functionality in ise like it was in quartus.
That worked! Thanks!