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    Taichi Ishitani
    @taichi-ishitani
    Hi @zhajio1988 ,
    Sorry for delay
    Jude Zhang
    @zhajio1988
    hi
    Taichi sang
    Taichi Ishitani
    @taichi-ishitani
    Hi @zhajio1988 ,
    I think my active time slot and your active time slot are different.
    On my second thought, can you post details of what you want to do on GitHub issue?
    chrisfreemanULPublic
    @chrisfreemanULPublic

    Hi @taichi-ishitani ,

    I've started using Rggen at Ultraleap and think it is going to be a great help with registers in our UVM testbenches. However Quartus is reporting an issue to do with packed enum types and I wondered if you have seen this?

    The error is line 76 of rggen_adapter_common.sv: "rggen_status [RESPONSES-1:0] status"
    Quartus says: "Error (10168): SystemVerilog Declaration error at rggen_adapter_common.sv(76): prefix for packed array type does not refer to a packable type"

    Someone had the same issue here, but with a very old version of Quartus: https://community.intel.com/t5/Intel-Quartus-Prime-Software/SystemVerilog-compile-error-when-casting/td-p/70689
    I'm using Quartus Prime Lite 19.1.0 on Ubuntu 20.04.1 LTS.

    Your code looks correct so I don't want to change it to unpacked if there is an easier solution (that can be shared with everyone too). Any ideas would be great, thanks.

    regards,
    Chris Freeman / Senior FPGA Engineer

    Taichi Ishitani
    @taichi-ishitani
    Hi @chrisfreemanULPublic ,
    Thank you for using RgGen!
    The latest common SV modules does not include this code. See this link:
    https://github.com/rggen/rggen-sv-rtl/blob/2e502b159b3f2ee64de3886ea4a7100118b80a8a/rggen_adapter_common.sv#L76
    Can you update them and try again?
    Taichi Ishitani
    @taichi-ishitani
    I think you're using the change_mux_implementation branch but not master branch.
    To get the latest common modules from the master branch, you need to execute following command:
    $ git checkout master
    $ git pull
    Taichi Ishitani
    @taichi-ishitani
    I've already confirmed that the latest common modules can be compiled by Quartus with no error.
    Taichi Ishitani
    @taichi-ishitani
    @chrisfreemanULPublic ,
    Let me know whether or not your compile error is fixed.
    chrisfreemanULPublic
    @chrisfreemanULPublic
    Hi, sorry for the slow reply! I got pulled onto another project. You're right, I was on that branch and it worked fix once I moved to master. Thanks for your help!
    Taichi Ishitani
    @taichi-ishitani
    Good!
    Please let me know if you have any questions, requests or feedback!
    Aaron Cook
    @cookacounty
    How do you use local versions of all the gems? For example I have cloned rggen, rggen-core, rggen-system-verilog but I can't figure out how to use my local versions of the dependancies. I tried bundle config set --local local.rggen-core ~/git/rggen/rggen-core but it didn't work
    You can run unit tests for each plugins by using rake command:
    For example:
    $ cd rggen-systemverilog
    $ rake spec
    Aaron Cook
    @cookacounty
    OK, I've cloned them all to the same directory, but now how to I run "rggen" pointing to all my local versions of each of these gems?
    Taichi Ishitani
    @taichi-ishitani
    If local clones exist then they will be loaded automatically.
    rggen-devtools is a repository for development tools e.g. Gemfile helpers, RSpec helpers.
    Auto loader feature is one of Gemfile helpers.
    Taichi Ishitani
    @taichi-ishitani
    YAML files on the rggen-checkout repository are to show dependent repositories.
    The above method will read a YAML file and add repositories to dependencies.
    Taichi Ishitani
    @taichi-ishitani
    https://qiita.com/taichi-ishitani/items/d89738b5376503c813d8
    This article shows how to add your own bit field type. I'm interpreting this article to English now.
    Taichi Ishitani
    @taichi-ishitani
    @cookacounty ,
    I put contributing guide.
    https://github.com/rggen/rggen/blob/master/CONTRIBUTING.md
    I hope this can help you to setup your working environment.
    megeed
    @megeed
    Hello, Is there a document that explains the external register interface with a timing diagram? thank you
    Taichi Ishitani
    @taichi-ishitani
    There is no such document. I will add it.
    Taichi Ishitani
    @taichi-ishitani
    Hi @megeed ,
    I added a document to describe the access protocol of external register type.
    https://github.com/rggen/rggen/wiki/Specification-for-RgGen-Bus-Interface-Protocol
    megeed
    @megeed
    Thank you
    megeed
    @megeed
    Hello, For sv outputs is there a way to have the register ports be automatically and systemverilog interface? Also is there a way to generate an instantiation template?
    Thank you
    Taichi Ishitani
    @taichi-ishitani
    Hi @megeed ,
    Currently, there are no such fetures.
    megeed
    @megeed
    Thank you
    megeed
    @megeed
    Hello, is there a pipeline option to easy timing? Thank you Sharief
    Taichi Ishitani
    @taichi-ishitani
    Hi @megeed ,
    Currently, there is no such option but you can edit common RTL modules to insert pipeline registers.
    https://github.com/rggen/rggen-sv-rtl
    Valera Marchenko
    @valera.marchenko96_gitlab
    Hi @taichi-ishitani
    i have a question
    is there a possibility to generate reg block with 2 if?
    first one is axi-lite for instance
    second something proprietary like wo with addr data wr_e signals
    Taichi Ishitani
    @taichi-ishitani
    Hi @valera.marchenko96_gitlab ,
    Currently, there is no such feature.
    You can create your own plugin to support such feature.