I've already confirmed that the latest common modules can be compiled by Quartus with no error.
Taichi Ishitani
@taichi-ishitani
@chrisfreemanULPublic , Let me know whether or not your compile error is fixed.
chrisfreemanULPublic
@chrisfreemanULPublic
Hi, sorry for the slow reply! I got pulled onto another project. You're right, I was on that branch and it worked fix once I moved to master. Thanks for your help!
Taichi Ishitani
@taichi-ishitani
Good! Please let me know if you have any questions, requests or feedback!
Aaron Cook
@cookacounty
How do you use local versions of all the gems? For example I have cloned rggen, rggen-core, rggen-system-verilog but I can't figure out how to use my local versions of the dependancies. I tried bundle config set --local local.rggen-core ~/git/rggen/rggen-core but it didn't work
YAML files on the rggen-checkout repository are to show dependent repositories. The above method will read a YAML file and add repositories to dependencies.
Hello, For sv outputs is there a way to have the register ports be automatically and systemverilog interface? Also is there a way to generate an instantiation template?
Thank you
Taichi Ishitani
@taichi-ishitani
Hi @megeed ,
Currently, there are no such fetures.
megeed
@megeed
Thank you
megeed
@megeed
Hello, is there a pipeline option to easy timing? Thank you Sharief
_
Taichi Ishitani
@taichi-ishitani
Hi @megeed , Currently, there is no such option but you can edit common RTL modules to insert pipeline registers. https://github.com/rggen/rggen-sv-rtl
Valera Marchenko
@valera.marchenko96_gitlab
Hi @taichi-ishitani
i have a question is there a possibility to generate reg block with 2 if?
first one is axi-lite for instance second something proprietary like wo with addr data wr_e signals
Taichi Ishitani
@taichi-ishitani
Hi @valera.marchenko96_gitlab , Currently, there is no such feature. You can create your own plugin to support such feature.