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  • May 28 13:42

    taichi-ishitani on master

    change URL of submodules (compare)

  • Sep 02 2020 09:00

    taichi-ishitani on master

    updated axi_vip submodule (compare)

  • Jul 14 2020 05:36
    gzhan88 closed #56
  • Jul 14 2020 05:36
    gzhan88 commented #56
  • Jul 13 2020 08:28
    taichi-ishitani commented #56
  • Jul 13 2020 04:42
    gzhan88 commented #56
  • Jul 13 2020 04:03
    taichi-ishitani commented #56
  • Jul 13 2020 03:58
    taichi-ishitani commented #56
  • Jul 13 2020 03:54
    taichi-ishitani commented #56
  • Jul 13 2020 03:46
    gzhan88 commented #56
  • Jul 13 2020 03:44
    taichi-ishitani commented #56
  • Jul 13 2020 03:42
    taichi-ishitani commented #56
  • Jul 13 2020 03:38
    gzhan88 opened #56
  • Jul 06 2020 02:21

    taichi-ishitani on master

    updated submodules (compare)

  • Mar 04 2020 03:35

    taichi-ishitani on svlint_on_github_actions_trial

    (compare)

  • Feb 21 2020 05:03

    taichi-ishitani on master

    use svlint-action (compare)

  • Feb 21 2020 05:00

    taichi-ishitani on master

    use svlint-action (compare)

  • Feb 21 2020 04:53

    taichi-ishitani on master

    use svlint-action (compare)

  • Feb 20 2020 05:17

    taichi-ishitani on changing_packet_format

    (compare)

  • Feb 20 2020 05:16

    taichi-ishitani on refactor_rtl_implementation

    (compare)

Taichi Ishitani
@taichi-ishitani
But I have no plant for this feature
coder-humbitious
@coder-humbitious
What about supporting various traffic classes throughout the fabric? Does it support it
Taichi Ishitani
@taichi-ishitani
traffic classes means read/write etc ?
coder-humbitious
@coder-humbitious
various virtual channels. Say normal priority, iso, niso, high priority iso, etc
Taichi Ishitani
@taichi-ishitani
OK, NoC has virtual channel feature
coder-humbitious
@coder-humbitious
Okay - how many channels etc are there. Is there a document to figure that out
Taichi Ishitani
@taichi-ishitani
but arbitration feature is round robin only
You can configure how many VCs are implemented
coder-humbitious
@coder-humbitious

Okay - that can be little more elaborate. RR, WRR, LRU etc.

Okay that is great

Taichi Ishitani
@taichi-ishitani
I also think more arbitration features are needed
You can configure number of VCs like above code
coder-humbitious
@coder-humbitious
Okay -

A documentation of all of these would have been really nice.

Are you willing to walk us through one day :) -

Taichi Ishitani
@taichi-ishitani
One day is difficult because my child is very young
I need to play with him
coder-humbitious
@coder-humbitious
One day means - some day. whenever you are free. May be 30 mins to 1 hr
We can quickly go over the files and which file does what functionality
Rest we can understand
Taichi Ishitani
@taichi-ishitani
OK
coder-humbitious
@coder-humbitious
I am actually not sure if it's rude to ask. Just saying
Okay - thanks Taichi. That will be great

Also, if we want to add IO coherence and convert your AXI4 driver/BFMs to ACE driver/BFMs, do you think that will be a good idea.

Or will you suggest to start us afresh

Taichi Ishitani
@taichi-ishitani
coherence and ACE support are good for me
coder-humbitious
@coder-humbitious
Okay - may be we can discuss it in that meeting. Which areas we should touch to support cache coherency verif
When will be free with 1 hr to spare. If you let me know the time and date, I will schedule a meeting in your Google Calendar
Taichi Ishitani
@taichi-ishitani
I'm free this time slot
coder-humbitious
@coder-humbitious
I see. So will tomorrow or Sat this time work ?
Taichi Ishitani
@taichi-ishitani
Tomorrow is good
coder-humbitious
@coder-humbitious
Okay - thanks Taichi. I will be ready with a VNC and will ping you tomorrow this time.
Taichi Ishitani
@taichi-ishitani
OK
coder-humbitious
@coder-humbitious
Will you please create a free account in Skype. I can call. Alternatively you can ISD to my India phone number (or I call you). Whatever works better.
Thanks a bunch for your time :-)
my skype - softw.free@gmail.com .
Taichi Ishitani
@taichi-ishitani
OK
I create a skype account
coder-humbitious
@coder-humbitious
Thanks. Bye. Good Night.
Taichi Ishitani
@taichi-ishitani
bye !
coder-humbitious
@coder-humbitious
Hi Taichi - another exercise might be having support for your tool in Verilator
Many modern CPU Cores as RISC-V etc support Verilator now.
We will also discuss about it. If you are interested, we can start that support activity.
Taichi Ishitani
@taichi-ishitani
RTL
I'm not sure verilator support TNoC RTL code
TB cannot be compilee by verilator
coder-humbitious
@coder-humbitious
Verilator supports SV latest AFAIK
Taichi Ishitani
@taichi-ishitani
Because TB is built on UVM
coder-humbitious
@coder-humbitious
I saw many RISC-V cores and even NVDLA open source core from NVIDIA run Verilator
They use UVM I think. Let me dig up a bit
coder-humbitious
@coder-humbitious

https://www.veripool.org/boards/2/topics/541-Verilator-Code-coverage-in-cc-mode

Taichi - I am afraid - Verilator doesn't support UVM SV.

It supports system-C

Taichi Ishitani
@taichi-ishitani
Yes, we need to create TB by using SystemC again if we use verilator