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  • Jan 04 22:08
    aignacio commented #28
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haykp
@haykp
hmm strange
seems it is short simulation
on my side it prints this and stops
( how to add code snippet?~)
image.png
image.png
Same behavioral for all tools - VCS, Xcelium and Questa(Modelsim)
Taichi Ishitani
@taichi-ishitani
haykp
@haykp
thanks
can you please share your simulation log
I will compare the logs
may be can find where is wrong
if possible both simulation and compile logs
Taichi Ishitani
@taichi-ishitani
sure.wait a moment
haykp
@haykp
thank you
Taichi Ishitani
@taichi-ishitani
haykp
@haykp
thanks
will compare now
Taichi Ishitani
@taichi-ishitani
I'd like you to share source files of tvip-axi which you're using if you can
haykp
@haykp
Sure
I forked from your repo
tue_master and tue, I just copied them
Taichi Ishitani
@taichi-ishitani
Thank you
haykp
@haykp
thanks
Taichi Ishitani
@taichi-ishitani
I will see your code
haykp
@haykp
thanks much
Taichi Ishitani
@taichi-ishitani
I tried to run your code and simulation finished successfully.
This is summary.
--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :    3
UVM_WARNING :    0
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[RNTST]     1
[SRANDOM]     1
[uvm_test_top]     1
$finish called from file "/storage/eda/tools/synopsys/VCS/P-2019.06-SP2-2/etc/uvm/base/uvm_root.svh", line 520.
$finish at simulation time             11607500
           V C S   S i m u l a t i o n   R e p o r t
Time: 11607500 ps
CPU Time:      2.670 seconds;       Data structure size:   0.9Mb
Thu Feb 25 15:08:29 2021

When compiling source files I got this warning.

Warning-[TEIF] Task enabled inside a function
/home/ishitani/workspace/temp/tvip-axi/src/tvip_axi_slave_driver.svh, 352
"this.do_nothing;"
  Task 'tvip_axi_slave_driver::do_nothing' is enabled inside function
  'tvip_axi_slave_driver::get_read_data_value', it may bring delays into the
  function.

I think you should fix it.

I'm not sure this warning causes your problem.
haykp
@haykp
seems now is okay, after fixing it
but getting this error:
{ ** Error: (vsim-3971) $cast to type 'class mtiUvm.uvm_pkg::uvm_sequence_base' from 'class work.tvip_axi_pkg::tvip_axi_master_item' failed in file D:/Documents/AXI_VIP/dev/tvip-axi/sample/env/tvip_axi_sample_write_read_sequence.svh at line 65.
#    Time: 7615500 ps  Iteration: 7  Region: /tvip_axi_sample_pkg::tvip_axi_sample_write_read_sequence::body 
}
haykp
@haykp
Would you please explain what is difference between SEQUENCER and SUB_SEQUENCER ?
Also why there is seperate WRITE_MONITOR and READ_MONITOR? Why not to keep one monitor?
virtual class tvip_axi_agent_base #(
  type  ITEM          = uvm_sequence_item,
  type  WRITE_MONITOR = uvm_monitor,
  type  READ_MONITOR  = uvm_monitor,
  type  SEQUENCER     = uvm_sequencer,
  type  SUB_SEQUENCER = uvm_sequencer,
  type  WRITE_DRIVER  = uvm_driver,
  type  READ_DRIVER   = uvm_driver
) extends tue_agent #( 
}
7 replies
Taichi Ishitani
@taichi-ishitani

tue_sequence_defines.svh

Can you copy this file to tue/src/macros and try again?
This may fix the above $cast error.

haykp
@haykp
sure, thank you much
Taichi Ishitani
@taichi-ishitani
Please let me know whether or not the $cast failure is fixed.
haykp
@haykp
Actually no, the issue still ther
# ** Error: (vsim-3971) $cast to type 'class mtiUvm.uvm_pkg::uvm_sequence_base' from 'class work.tvip_axi_pkg::tvip_axi_master_item' failed in file D:/Documents/AXI_VIP/dev/tvip-axi/sample/env/tvip_axi_sample_write_read_sequence.svh at line 65.
#    Time: 7615500 ps  Iteration: 7  Region: /tvip_axi_sample_pkg::tvip_axi_sample_write_read_sequence::body }
Taichi Ishitani
@taichi-ishitani
Did you copy the file correctly?
Taichi Ishitani
@taichi-ishitani
or can you replace tue_do_with macro to uvm_do_with macro and try again?
haykp
@haykp
okay let me replace and get back to you
Konstantin Kurenkov
@kkurenkov

I run your sample test
tvip-axi/sample/work/makefile

TESTS = default

and watch transaction in slave interface

uvm_test_top.slave_agent.sequencer@@tvip_axi_slave_default_sequence transaction

-------------------------------------------------------------------------------------
Name                      Type                      Size  Value                      
-------------------------------------------------------------------------------------
axi_item                  tvip_axi_slave_item       -     @8174                      
  access_type             tvip_axi_access_type      32    TVIP_AXI_WRITE_ACCESS      
  id                      integral                  32    'hd7                       
  address                 integral                  64    'h3b82999286c2             
  burst_length            integral                  32    'd78                       
  burst_size              integral                  32    'd8                        
  burst_type              tvip_axi_burst_type       2     TVIP_AXI_INCREMENTING_BURST
  qos                     integral                  4     'd5                        
  data                    da(integral)              0     -                          
  strobe                  da(integral)              0     -                          
  response                array(tvip_axi_response)  1     -                          
    [0]                   tvip_axi_response         2     TVIP_AXI_OKAY              
  start_delay             integral                  32    'd0                        
  write_data_delay        da(integral)              0     -                          
  response_delay          da(integral)              1     -                          
    [0]                   integral                  32    'd0                        
  address_ready_delay     integral                  32    'd0                        
  write_data_ready_delay  da(integral)              78    -                          
    [0]                   integral                  32    'd0                                           
    ...                   ...                       ...   ...                        

    [77]                  integral                  32    'd0                        
  response_ready_delay    da(integral)              0     -                          
  address_begin_time      time                      64    102000                     
  address_end_time        time                      64    102000                     
  write_data_begin_time   time                      64    102000                     
  write_data_end_time     time                      64    0                          
  response_begin_time     time                      64    0                          
  response_end_time       time                      64    0                          
  begin_time              time                      64    102000                     
-------------------------------------------------------------------------------------

in this transaction i can't see data
How can i receive data in this case?

Taichi Ishitani
@taichi-ishitani
tvip_axi_monitor_base::end_response is a suitable location to print transaction info.
https://github.com/taichi-ishitani/tvip-axi/blob/5e33a130d74e3514fa06e6eaca3a1628d9fb6df5/src/tvip_axi_monitor_base.svh#L58
Taichi Ishitani
@taichi-ishitani
Insert uvm_info to this location then you can see all transaction info.
mudgun1983
@mudgun1983
Hi @taichi-ishitani . While invoking the RALF , add code like this:
sys_tsn_switch_reg_model_axi.default_map.set_sequencer(tvip_axi_env0.master_sequencer, reg2axi_bus);
sys_tsn_switch_reg_model_axi.default_map.set_auto_predict(1);
The write channel is blocked
image.png
mudgun1983
@mudgun1983
Could you please share an ralf example ,thank you very much
Taichi Ishitani
@taichi-ishitani
@mudgun1983
This TB is an example for UVM RAL integration.
https://github.com/rggen/rggen-sample-testbench