Where communities thrive


  • Join over 1.5M+ people
  • Join over 100K+ communities
  • Free without limits
  • Create your own community
People
Activity
    Irvise
    @irvise:matrix.org
    [m]
    I would suspect that it should be created (by default or behind a flag) during synthesis.
    That would greatly help me with my project (https://github.com/AdaCore/svd2ada also works with RISC-V).
    Dolu1990
    @Dolu1990

    @irvise:matrix.org

    Question: is there a way to generate a CMSIS-SVD descriptor of the VexRiscv CPU / SaxonSOC platform?

    There is nothing in place actualy. It would be cool to have, but actualy, the dev was focused on other aspects (linux, more peripherals, mooore power, ..)

    Irvise
    @irvise:matrix.org
    [m]
    So I take it that the C headers with the addresses and such, were handcrafted no?
    Rob Taylor
    @rob_chipflow:matrix.org
    [m]
    @Dolu1990: Is there a pregenerated vexriscv or murex around? I have a team that wants to use it to test some FPGA tooling
    Lawrie Griffiths
    @lawrie
    The BSP generator could probably be extended to generate a CMSIS-SVD descriptor. I have been doing some work for Rust recently and an svd file would help a lot in generating a Rust HAL for SaxonSoc.
    Lawrie Griffiths
    @lawrie
    I think Litex Vexriscv does generate an svd file - see http://pepijndevos.nl/2020/08/04/a-rust-hal-for-your-litex-fpga-soc.html
    1 reply
    Lawrie Griffiths
    @lawrie
    @rob_chipflow:matrix.org What is it that you want? Is it pregenerated Verilog or a prebuilt bitstream for a device such as the Ulx3s?
    Is it Murax that you want rather than the much newer SaxonSoc, and if so is it any particular SoC configuration?
    Lawrie Griffiths
    @lawrie
    There are some rather old VexRiscv generated verilog files here - https://github.com/m-labs/VexRiscv-verilog, but I believe those are designed to be used with a Wishbone bus and Litex peripherals.
    Rob Taylor
    @rob_chipflow:matrix.org
    [m]
    lawrie (Lawrie Griffiths): hi, it’s some generated verilog for the FABulous open fpga folk to try out on their tooling
    I guess for now a minimal test case would be great - I’ve shared the old m-labs ‘lite’ verilog with them, but we could do with a modern light generated configuration
    Their rather against the clock, so they’re trying to avoid learning new tools at this point... :)
    Lawrie Griffiths
    @lawrie
    You might get a quicker reply from @Dolu1990 on the Vexriscv gitter - https://gitter.im/SpinalHDL/VexRiscv
    Lawrie Griffiths
    @lawrie
    @rob_chipflow:matrix.org I could put the generated files for the Ulx3sMininal SaxonSoc configuration in a repository. That runs the blinkAndEcho standalone software and uses a uart and gpio. It needs some *.bin files as well as the .v file. As with any generated file it is somewhat specific to the board it was generated for, but if you can give it a 25Mz clock, an n_reset pin, RX and TX pins for the uart, 8 gpio pins (for the led) and some Jtag pins, it would probably run on another board.
    7 replies
    Radu Stoichita
    @radu_stoichita_gitlab
    @lawrie remember what kind of computer guided apollo to the moon 😅
    Other Tim
    @tcal-x
    @rob_chipflow:matrix.org , there is also VexRiscv pre-generated Verilog here -- https://github.com/litex-hub/pythondata-cpu-vexriscv/tree/master/pythondata_cpu_vexriscv/verilog -- which may be more recent than the m-labs versions. As noted before, they are generated with a Wishbone interface for LiteX. It's fairly easy to clone this repo and then modify the Makefile/buildscript and build a new VexRiscv to customize for what you want, although you would need to install sbt.
    Dolu1990
    @Dolu1990
    @rob_chipflow:matrix.org There is no pregenerated SoCs as far as i know
    1 reply
    irvise
    @irvise:matrix.org
    [m]
    2 replies
    If someone is interested on how it was made, I can copy-paste what I just sent to the Ada group.
    And if you are C programmers I can show you how amazing, simple and clean the code is :)
    Irvise
    @irvise:matrix.org
    [m]
    And good news. The connection errors that I was getting happened because I was using a very outdated version ob sbt. Funny that OpenSuse Tumbleweed had such an old version in its repos.
    e2kgh
    @e2kgh
    @irvise:matrix.org : I would be very interested in the code. You have a git somewhere with it?
    Irvise
    @irvise:matrix.org
    [m]
    @e2kgh: sure, I am preparing it. I will send you the link shortly.
    Hi. Is someone getting the same error when building buildroot?
    libfakeroot.c: In function ‘statx’:
    libfakeroot.c:102:50: error: ‘_STAT_VER’ undeclared (first use in this function)
      102 | #define INT_NEXT_FSTATAT(a,b,c,d) NEXT_FSTATAT64(_STAT_VER,a,b,c,d)
          |                                                  ^~~~~~~~~
    fakerootconfig.h:15:53: note: in definition of macro ‘NEXT_FSTATAT64’
       15 | #define NEXT_FSTATAT64(a,b,c,d,e) next___fxstatat64(a,b,c,d,e)
          |                                                     ^
    libfakeroot.c:2473:5: note: in expansion of macro ‘INT_NEXT_FSTATAT’
     2473 |   r=INT_NEXT_FSTATAT(dirfd, path, &st, flags);
          |     ^~~~~~~~~~~~~~~~
    make[4]: *** [Makefile:659: libfakeroot.lo] Fehler 1
    make[3]: *** [Makefile:677: all-recursive] Fehler 1
    make[2]: *** [Makefile:452: all] Fehler 2
    make[1]: *** [package/pkg-generic.mk:250: /home/fernando/Dirt/ULX3S/Ulx3sSmp/buildroot-build/build/host-fakeroot-1.25.3/.stamp_built] Fehler 2
    1 reply
    This is a freshly cloned repo following the instructions as per the README here: https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.3/bsp/radiona/ulx3s/smp
    Using 32Mb for RAM, with FPU, 2 cores and a 85F FPGA.
    But I can confirm that that error happens without the FPU too. And it does not seem related at all.
    Irvise
    @irvise:matrix.org
    [m]
    Just ignore the badly designed .gpr file. It is still a work in progress.
    Irvise
    @irvise:matrix.org
    [m]
    I have cloned version 2021.02.X of buildroot. And it does not work because there is a legacy option in the config file for the ulx3s in buildroot-saxon-... config: BR2_BINUTILS_VERSION_2_33_X=y. Commenting it out makes it work again.
    And that option seems to be left out, since there are variables activating the use of newer binutils.
    Irvise
    @irvise:matrix.org
    [m]
    Sorry for the plethora of messages. But I suppose this is to be expected, is it not?
    >>>   Executing post-image script /home/fernando/Dirt/ULX3S/Ulx3sSmp/buildroot-spi
    /home/fernando/Dirt/ULX3S/Ulx3sSmp/buildroot-spinal-saxon/boards/common/../spinal-
    INFO: cmd: "mkdir -p "/home/fernando/Dirt/ULX3S/Ulx3sSmp/buildroot-build/build/gen
    INFO: cmd: "rm -rf "/home/fernando/Dirt/ULX3S/Ulx3sSmp/buildroot-build/build/genim
    INFO: cmd: "mkdir -p "/home/fernando/Dirt/ULX3S/Ulx3sSmp/buildroot-build/build/gen
    INFO: cmd: "cp -a "/home/fernando/Dirt/ULX3S/Ulx3sSmp/buildroot-build/target" "/ho
    INFO: cmd: "find '/home/fernando/Dirt/ULX3S/Ulx3sSmp/buildroot-build/build/genimagirt/ULX3S/Ulx3sSmp/buildroot-build/target/{}' '/home/fernando/Dirt/ULX3S/Ulx3sSmp/
    INFO: cmd: "mkdir -p "/home/fernando/Dirt/ULX3S/Ulx3sSmp/buildroot-build/images"" 
    INFO: vfat(boot.vfat): cmd: "dd if=/dev/zero of="/home/fernando/Dirt/ULX3S/Ulx3sSm
    INFO: vfat(boot.vfat): cmd: "mkdosfs   '/home/fernando/Dirt/ULX3S/Ulx3sSmp/buildro
    sh: Zeile 1: mkdosfs: Kommando nicht gefunden.
    INFO: vfat(boot.vfat): cmd: "rm -f "/home/fernando/Dirt/ULX3S/Ulx3sSmp/buildroot-b
    ERROR: vfat(boot.vfat): failed to generate boot.vfat
    That is how my saxon_buildroot ended. My system does not have mkdosfs.
    emard
    @emard
    @lawrie I just downloaded ulx3s_zx81 and it still compiles and works with latest tools, just a small future-proof check :)
    Lawrie Griffiths
    @lawrie
    @emard Not sure why you are testing that. I did push some minor changes to it as I had not put working versions of the ZX80 and ZX81 in my ulx3s_bit_streams repository and when I build them, I noticed I had some minor uncommitted changes. Are you working on new boards at the moment?
    @irvise:matrix.org Not sure what caused your original buildroot failure. I use Ubuntu 20.04. I don't know which Linux version @Dolu1990 is using. Your latest error is in the code that builds the sd card image, and that is optional as there are instructions for building the SD card manually.
    Irvise
    @irvise:matrix.org
    [m]
    The error was caused in the end because my system does not have mkdosfs. OpenSuse dropped it (symlinks it) to mkfs.fat. However, it seems that they have stopped doing that too.
    I got it loaded in the end :) However, there seems to be an issue with u-boot from buildroot 2021.02.X. It never actually loaded anything.
    In the end I loaded your premade u-boot and it works now. Though at the beginning it was having a lot of issues loading files. Now, after a couple of reflashes, it seems it works beautifully.
    emard
    @emard
    @lawrie ok ZX81 shows picture and K-prompt, should be ok, just a friend undusted old ZX81 in wooden box and real kbd so I got idea... New board v3.1.6 design PCB prototype is produced, parts for few boards are ready, Goran and I expect soon assembly and we will test. WROVER onboard, more useable pins shared with FPGA and few other minor changes like 8-pin LCD/OLED header shared with serdes-in for experiments. (but it is still too undocumented, my wish is HDMI-IN one day if it ever gets hacked that far as HDMI is not officially listed as supported protocol)
    Dolu1990
    @Dolu1990
    @irvise:matrix.org Maybe sudo apt install dosfstools -y would fix it ?
    I never had this issue, likely i installed the depedancies tools prior to building buildroot
    Hooo mkdosfs i see XD
    jamon
    @jamon
    Curious if anyone has ideas on how I might be able to get this to work--I'm using a very small verilog module that likely was designed for other toolchains, it's a parameterized (variable width) priority encoder (think 16 bit in, binary output for most or least significant bit number that was on). It uses a "wor" (wide or) to accomplish this, which yosys seems fine with, but nextpnr-ecp5 doesn't like and gives this error: ERROR: cell type '$or' is unsupported (instantiated as '$auto$hierarchy.cc:1196:execute$383')
    the culprit line in the verilog is this output wor [WIDTH-1:0] binary_out
    if anyone has ideas on how I can make that work, or if they have suggestions on other techniques to get a parameterized variable width priority encoder, I'd be super appreciative
    jamon
    @jamon
    it's always right after you figure out how to word something in a question, you get the idea to google it differently and find something--I've got it working now, using a different solution I found here (in case anyone else is looking for something similar ever): https://stackoverflow.com/questions/38230450/first-non-zero-element-encoder-in-verilog