Where communities thrive


  • Join over 1.5M+ people
  • Join over 100K+ communities
  • Free without limits
  • Create your own community
People
Activity
    kost
    @kost
    So, you can say something like:
    webreplcmd --host 192.168.4.1 --password ulx3s cmd 'import ecp5; ecp.prog("http://my.fpga.dir/bitstream.bit)'
    Lawrie Griffiths
    @lawrie
    @emard When I try to build it, it does not find spi_controller_MIST.vhd
    Lawrie Griffiths
    @lawrie
    If Iget rid of "_MIST" in the Makefile, it builds and runs basic programs.
    Lawrie Griffiths
    @lawrie
    A disk containing dos33master.nib seems to be ignored to me and it goes straight to the basic prompt.
    Lawrie Griffiths
    @lawrie
    The code in the repository has both the disk and sdcard code omitted (if false generate). When I included them, it was too big for a 12F, so I am now running it on my 85F.
    Lawrie Griffiths
    @lawrie
    It is now doing the same as for you. It hangs unless I press button 0. It makes no difference if an sd card is inserted or not.
    emard
    @emard
    Yes this _MIST is rewrite of := replaced with <= I found on on other github port of apple2fpga, it seems the the same. My theory is that SD card is not working or compatible, so it spi_controller waits indefinitely to read first track.
    Lawrie Griffiths
    @lawrie
    Yes, I came to a similar conclusion. I think it is just not working at all for some reason, rather than it being a card compatibility problem.
    Lawrie Griffiths
    @lawrie
    I was considering putting some diagnostics in the spi controller to see what state it gets stuck in and what commands it sends with what results. I had more problems getting the sd card working with SaxonSoc than anything else, and am still not entirely sure what the problems were or how I fixed them. Keeping the ESP32 in reset fixed at least one of the problems I had, but with micropython on the ESP32, I have not had any sd card problems with SaxonSoc .
    Lawrie Griffiths
    @lawrie
    @Dolu1900 now has his 12F board and is getting SaxonSoc working on it. So we should get better SDRAM performance and reliability, a better serial driver and fewer slices used with him working on it.
    I need to learn VHDL better , as quite a lot of projects on the Ulx3s use it. I have stuck with Verilog and SpinalHDL up to now. I am going to have to learn Migen sometime, as well.
    emard
    @emard
    Great that board arrived to Dolu, yes faster SDRAM would improve everything! Almost all opensource/amateur projects I download are in VHDL but most of them actually write verilog style in vhdl syntax, pass that thru vhd2vl and it will still work :). Only one that uses advanced VHDL is hdl4fpga scopeio, this core really demonstrates how vhdl can be compact and powerful.
    I have found "suspect", it's 2MHz LUT-generated clock that is currently used as clock source but should be changed to clock enable instead. LUT generated clocks are very unreliable at lattice chips
    Goran Mahovlic
    @goran-mahovlic
    @lawrie Yesterday I have shipped 12F to Roman ...
    Lawrie Griffiths
    @lawrie
    @goran-mahovlic Thanks.
    Paul Ruiz
    @pnru_gitlab
    @kost Great script, many thanks!
    kost
    @kost
    Thanks @pnru_gitlab . BTW apio and icestudio pull requests were accepted. So, apio and icestudio in develop branch support ulx3s. Actually, first ecp5 board supported. https://github.com/FPGAwars/apio and https://github.com/FPGAwars/icestudio
    Lawrie Griffiths
    @lawrie
    @emard I tried the orao computer. It mainly says "NEPRAVILAN UNOS" , but I did manage to get into BASIC.
    Dobrica Pavlinušić
    @dpavlin
    NEPRAVILAN UNOS == syntax error in croatian
    @lawrie I'm trying to build SaxxonSOC using makefile.uboot85 but after make generate, make fails with ERROR: Module \USRMCLK' referenced in module\Ulx3sLinuxUboot' in cell `\ulx3sUsrMclk' is not part of the design.
    any hints to what am I doing wrong?
    Lawrie Griffiths
    @lawrie
    Do you have the latest versions of trellis, yosys and nextpnr-ecp5?
    Dobrica Pavlinušić
    @dpavlin
    i suspected that, so I'm recompiling as we speak :-)
    Lawrie Griffiths
    @lawrie
    @Dolu1990 was building it yesterday and found he needed the latest version of everything to meet the 50MHz timing.
    I believe USRMCLK ought to be included with the latest version of yosys.
    Lawrie Griffiths
    @lawrie
    BTW, thanks for the corrections to my READMEs.
    Dobrica Pavlinušić
    @dpavlin
    Glad I can help.
    Lawrie Griffiths
    @lawrie
    Adding references to how to build yosys and nextpnr-ecp5 might be useful in the build from source README.
    Dobrica Pavlinušić
    @dpavlin
    How hard would it be to add i2c to linux? I'm thinking about rtc... If nothing else we could use gpio driver for it... This is my first SpinalHDL exposure, so I'm trying to set resonable goal for me :-)
    First step for me however, will be to add leds to kernel /sys/class/leds so we can get nice triggers (like network traffic or cpu usage) on leds -- it should mainly be kernel re-compile and device tree modification to make it work since gpio is already there :-)
    Lawrie Griffiths
    @lawrie
    It should not be that hard. I have i2c in SaxonSoc in other projects such as https://github.com/SpinalHDL/SaxonSoc/blob/dev/hardware/scala/saxon/board/blackice/BlackiceSocArduino.scala#L25
    Dobrica Pavlinušić
    @dpavlin
    thanks, I will have a look and report progress :-)
    Lawrie Griffiths
    @lawrie
    That is just i2c master which should be sufficient for driving the rtc.
    Then you will need the dts entry and to include i2c in the kernel. If I were doing it, I would look at how i2c is done in the Raspberry Pi.
    Dobrica Pavlinušić
    @dpavlin
    I have quite a lot of device tree and u-boot expirience, this should not be a problem :-)
    Lawrie Griffiths
    @lawrie
    The generated board support packages include a generated dts, but it is not used yet and the simple i2c generator that I wrote does not generate the dts.
    I don't have much experience in u-boot or device trees.
    Dobrica Pavlinušić
    @dpavlin
    reading through chat, I figured that this is a part in which I can help somewhat :-)
    Lawrie Griffiths
    @lawrie
    There is a problem building SaxonSoc Linux, that some build randomly do not work. It seems to be something to do with SDRAM access.
    @Dolu1990 is about to redo the SDRAM access for the Ulx3s, which should make it more reliable and faster, as he plans to support double frequency access.
    There is a lot of information on the development of the u-boot version here , which might be useful to you - SpinalHDL/SaxonSoc#7
    Lawrie Griffiths
    @lawrie
    I2c Linux support will also need a spinal.lib driver here - https://github.com/SpinalHDL/linux/tree/linux-5.0.y/drivers/i2c
    You may need help from @Dolu1990 with that.
    Or as you say, you could probably bit-bang i2c with gpio.
    The terasic De1Soc version of SaxonSoc Linux has a dts entry for an led for disk access - https://github.com/SpinalHDL/buildroot/blob/saxon/board/spinal/saxon_default/spinal_saxon_default_de1_soc.dts#L194
    Dolu1990
    @Dolu1990
    Right about I2C in linux, i also suggest to go to i2c-gpio driver
    Lawrie Griffiths
    @lawrie
    We really need a better GPIO mapping for the Ulx3s. That might involve including adding a second gpio peripheral to the hardware (gpioB) and doing a better lpf file mapping to pins. It might mean increasing the niumbers of pins that support interrupts. It would be good to include access to the buttons and switches and to make it easy to add Pmods that need interrupt support like the enc28j60 one.
    Dobrica Pavlinušić
    @dpavlin
    thanks, my problem was indeed too old nextpnr/yosys.
    Goran Mahovlic
    @goran-mahovlic
    USB.png