So if you don't use self reconfiguration (no idea how that might be useful,as a n00b I don't really understand this) you set it to DISABLE
That's how I interpret the datasheet but I may be wrong :)
If user design needs to access FLASH (from running bitstream), MASTER_SPI_PORT=DISABLE must be there. Such bitstream must be stopped before JTAG can access FLASH. If ENABLE'd, then bitstream can't access FLASH but JTAG can then R/W FLASH while bitstream is running (not need to stop bitstream). By default JTAG programmers first send JTAG commands to stop currenty running bitstream and then flash, in order not to confuse the user.
Ahaa right, thanks emard!
@emard Have you tried adding support for a native USB keyboard to the us2 connector?
Maybe I should get working on building Micropython 1.12 with IP forwarding enabled. It seems that 1.12 has support for bluetooth (1.11 does not). Maybe it offers a simple way to add a wireless keyboard and mouse.
Yes, these bluetooth keyboard/mouse projects look promising! In meantime I was playing with e-ink displays and RTC from micropython. Also made i2c bidirectional bridge in FPGA (not trivial to make)
Hello, I wanted to have a 90 degree shifted clock. I was trying out the ecp5pll from @emard. I get it running and the clock adjustment seems to work, but somehow it does not get shifted for me. Is this currently not working with yosys and so forth, is there anything I have to take care of, or might it just be a bug on my side? Tried to search this chat a bit and just searched a bit on the internet but the things I found about it were quite old and not necessarily about my problem. Any ideas? I am using the vhdl version btw
I have taken some time off implementing computers from 1984 to look at GPUs, and any Verilog implementations that I could find. If I am ever to implement computers from the mid-nineties onwards, I need to understand 3D GPUs. I found this which is very interesting - https://github.com/jbush001/NyuziProcessor. It is a CPU that implements general-purpose GPU (GPGPU) single-instruction multiple-data (SIMD) code, and which can be used to implement rasterization, shading etc. in software. It comes with a C compiler and is a general-purpose language that has been used to implement a variant of Unix and Doom. I am not sure if it will fit on an 85f. It looks exactly what I was looking for in an open source GPU.
The author (Jeff Bush) has a blog on it as well - https://jbush001.github.io/, which has more interesting stuff on GPUs including a full description of the the Raspberry Pi one, and a reference to another verilog GPU implementation.
I also looked at Jeff Bush's other repositories and found that I had ported one previously to an ice40 board - his Lisp FPGA implementation.
I also found this interesting project, which I have ported to the ulx3s -https://github.com/lawrie/FPGAWhack. It is also a type of parallel processing GPU,. with a CPU and an assembler, but the source of data is effectively limited to the x, y co-ordinates of a pixel and a frame number. There is a compiler (in python) that lets you enter an expression involving x, y and f, which calculates the pixel color. It can be used to generate interesting graphical output. There is more detail here - https://github.com/jbush001/FPGAWhack/wiki
@lawrie HI lawrie, great GPU-vacation. 85F is large and rare project use it fully and compile time will rise significantly so a part of preparation could be getting a free login on some supercomputing cluster for yosys compilation. Here is DOOM for ULX3S and 1h compile time on normal PC https://twitter.com/sylefeb/status/1288053013748289538
@daveshah1 can yosys actually split its processing on parallel cluster to get any speedup?
you could in theory process submodules separately but you would get a less optimal result that way
For a larger project like GPU that could be good option