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    So if you don't use self reconfiguration (no idea how that might be useful,as a n00b I don't really understand this) you set it to DISABLE
    That's how I interpret the datasheet but I may be wrong :)
    emard
    @emard
    If user design needs to access FLASH (from running bitstream), MASTER_SPI_PORT=DISABLE must be there. Such bitstream must be stopped before JTAG can access FLASH. If ENABLE'd, then bitstream can't access FLASH but JTAG can then R/W FLASH while bitstream is running (not need to stop bitstream). By default JTAG programmers first send JTAG commands to stop currenty running bitstream and then flash, in order not to confuse the user.
    Rangel Ivanov
    @ironsteel
    Ahaa right, thanks emard!
    Rangel Ivanov
    @ironsteel
    @emard Have you tried adding support for a native USB keyboard to the us2 connector?
    Or is it too much of a pain to implement?
    emard
    @emard
    @ironsteel Yes I have USB KBD example in both verilog and vhdl here https://github.com/emard/ulx3s-misc/tree/master/examples/usb/proj/lattice/ulx3s/usbhid_host
    emard
    @emard
    PS/2 core is small, compiles fast so it's sometimes less effort to find PS/2 keyboard than to adapt USB scancodes to matrix encoders that expect PS/2 protocol
    Having my USB core, most USB low-speed keyboards on US2 port will technically work without any problem, hotpluggable and reliable
    Rangel Ivanov
    @ironsteel
    Cool! Thanks! I'm trying it right now
    emard
    @emard
    I will see also, maybe I have to refresh this example if broken when shared files with other projects have been upgraded
    Rangel Ivanov
    @ironsteel
    I had some problems finding the lcd_video.v file but I've copied it from another directory in the repo
    Rangel Ivanov
    @ironsteel
    I've got it working, tested it with a usb mouse and its working
    emard
    @emard
    Great! I have to refresh this example to compile out of the box.
    use .C_report_length_strict(1), to filter out some noise which will occassionally be reported
    .C_report_length(8) should be for all standard keybards
    Rangel Ivanov
    @ironsteel
    thanks! So trying it with a keyboard that has some multimedia buttons on it, but it doesn't initialize
    will poke around alittle bit and see if I can get it working
    emard
    @emard
    Such keyboard could be a USB composite device. Plug it in linux and find out endpoint number which reports the main keyboard keys
    I have one keyboard that runs USB protocol well but doesn't report any key to my driver
    Rangel Ivanov
    @ironsteel
    Yes it is a composite device. lsusb gives me several endpoints
    emard
    @emard
    You can try each IN endpoint in my driver so maybe one will just work C_report_endpoint=N
    Rangel Ivanov
    @ironsteel
    Thanks!
    emard
    @emard
    I did some maintenance on usb-hid example to use ecp5pll, did some cleanup fixing etc
    kost
    @kost
    kost
    @kost
    updated toolchain with silice
    pnrhub
    @pnrhub
    Maybe I should get working on building Micropython 1.12 with IP forwarding enabled. It seems that 1.12 has support for bluetooth (1.11 does not). Maybe it offers a simple way to add a wireless keyboard and mouse.
    emard
    @emard
    https://www.youtube.com/watch?v=aK93u340A9I this should be possible but I haven't tried
    Ups this is wireless USB, must search better example
    emard
    @emard
    Yes, these bluetooth keyboard/mouse projects look promising! In meantime I was playing with e-ink displays and RTC from micropython. Also made i2c bidirectional bridge in FPGA (not trivial to make)
    Ghost
    @ghost~5dc3e397d73408ce4fd042cd
    Hello, I wanted to have a 90 degree shifted clock. I was trying out the ecp5pll from @emard. I get it running and the clock adjustment seems to work, but somehow it does not get shifted for me. Is this currently not working with yosys and so forth, is there anything I have to take care of, or might it just be a bug on my side? Tried to search this chat a bit and just searched a bit on the internet but the things I found about it were quite old and not necessarily about my problem. Any ideas? I am using the vhdl version btw
    emard
    @emard
    There's some order of signals and small delays between them for dynamic shifting to work. https://github.com/emard/ulx3s-misc/blob/master/examples/sdram/memtest_mister/hdl/top/top_memtest.v#L73 here is module to control phase shifts by pressing of BTN for testing of SDRAM with variable phase shift of the clock to chip
    Ghost
    @ghost~5dc3e397d73408ce4fd042cd
    alright, ill look at that. thanks
    Ghost
    @ghost~5dc3e397d73408ce4fd042cd
    Oh nice it works. My thinking was just a bit wrong and there was a little bug too. Thanks
    emard
    @emard
    ecp5pll has possibility for fine-precision phase adjustment but this simple BTN module doesn't generate proper phaseloadreg signal https://github.com/emard/ulx3s-misc/blob/master/examples/sdram/memtest_mister/hdl/btn_ecp5pll_phase.v#L51
    emard
    @emard
    I have done a low power shutdown and wake-on-RTC clock example https://github.com/emard/ulx3s-misc/tree/master/examples/rtc/micropython-mcp7940n with this e-ink display shows picture without power https://github.com/emard/ulx3s/blob/master/doc/MANUAL.md#e-inke-paper-display
    Lawrie Griffiths
    @lawrie
    I have taken some time off implementing computers from 1984 to look at GPUs, and any Verilog implementations that I could find. If I am ever to implement computers from the mid-nineties onwards, I need to understand 3D GPUs. I found this which is very interesting - https://github.com/jbush001/NyuziProcessor. It is a CPU that implements general-purpose GPU (GPGPU) single-instruction multiple-data (SIMD) code, and which can be used to implement rasterization, shading etc. in software. It comes with a C compiler and is a general-purpose language that has been used to implement a variant of Unix and Doom. I am not sure if it will fit on an 85f. It looks exactly what I was looking for in an open source GPU.
    The author (Jeff Bush) has a blog on it as well - https://jbush001.github.io/, which has more interesting stuff on GPUs including a full description of the the Raspberry Pi one, and a reference to another verilog GPU implementation.
    I also looked at Jeff Bush's other repositories and found that I had ported one previously to an ice40 board - his Lisp FPGA implementation.
    Lawrie Griffiths
    @lawrie
    I also found this interesting project, which I have ported to the ulx3s -https://github.com/lawrie/FPGAWhack. It is also a type of parallel processing GPU,. with a CPU and an assembler, but the source of data is effectively limited to the x, y co-ordinates of a pixel and a frame number. There is a compiler (in python) that lets you enter an expression involving x, y and f, which calculates the pixel color. It can be used to generate interesting graphical output. There is more detail here - https://github.com/jbush001/FPGAWhack/wiki
    emard
    @emard
    @lawrie HI lawrie, great GPU-vacation. 85F is large and rare project use it fully and compile time will rise significantly so a part of preparation could be getting a free login on some supercomputing cluster for yosys compilation. Here is DOOM for ULX3S and 1h compile time on normal PC https://twitter.com/sylefeb/status/1288053013748289538
    @daveshah1 can yosys actually split its processing on parallel cluster to get any speedup?
    David Shah
    @daveshah1
    No
    you could in theory process submodules separately but you would get a less optimal result that way
    emard
    @emard
    For a larger project like GPU that could be good option