// Bit definitions: // 31 Read / not write. // 30 Repeated Start. On read cycles setting this bit uses repeated start instad // 29:23 Reserved. // 22:16 7-bit I2C address of slave. // 15:8 Register Subaddress // 7:0 Data to write. Don't care on read cycles. //reg [31:0] status; // I2C status register // Bit definitions // 31 Busy. Not ready to accept new control register writes. // 30 Address NACK. Last address cycle resulted in no acknowledge from slave. // 29 Data NACK. Last data write cycle resulted in no acknowledge from slave. // 28 Read. Most recently completed cycle was a read. Data in bits 7:0 is valid. // 27 Overrun. An attempt was made to write the ctrl_reg while busy. Cleared // on successful write of ctrl_reg. // 26 Initializing - waiting for SDA to go high after module reset // 25:8 Reserved. Tied to zero. // 7:0 Read data. Valid after a read cycle when bit 28 is set.
@emard I integrated your i2c module into the cortex (see https://gitlab.com/pnru/ulx3s-misc/-/blob/master/tmp/sys.v). It does not seem to work for me, but maybe I'm using it wrong. I also - and I really should not have - went down the rabbit hole and wrote an I2C master from scratch (see https://gitlab.com/pnru/ulx3s-misc/-/blob/master/tmp/i2c.v). It also does not seem to work for me.
When I look at the wave forms in Icarus/GTKWave I think both bits of code are producing very similar signals that should work (at least in my current understanding or I2C and the MCP7940). Your code is more careful to debounce the SCL and SDA signals. It also seems to have an I2C bus reset that I don't have (Start followed by Stop, with no clocks in between.) A 3rd difference is that I'm running SCL at ~400KHz and you are is using ~1Mhz
I really need to get back to real work, but if someone wants to take a look at and do a code or GTKWave review over the next days, I'd be grateful.