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    Lawrie Griffiths
    @lawrie
    The last daily build that builds the QL correctly is August 7th. August 8th fails.
    Lawrie Griffiths
    @lawrie
    I wonder if it could be this change - YosysHQ/yosys@9a4f420 and related ones done on the same day.
    Lawrie Griffiths
    @lawrie
    I notice that the OrangeCrab examples site says that there is a Yosys bug affecting LiteX SoCs and that you to use a version before July 1st to avoid that.
    Lawrie Griffiths
    @lawrie
    I tried the prebuilt Circuitpython examples from the OrangeCrab. That is built with LiteX and VexRiscv. I wonder if that could be ported to the Ulx3s. Then we could have Circuitpython running on the ESP32 and the FPGA :)
    emard
    @emard
    If circuitpython would be more ready I would redesign PCB for ESP32-S2 already. No wifi, no SD, commandline bugs, basic things unstable and even linux crashes too. Currenty SPI is broken too. adafruit/circuitpython#3339 But last known good release without PSRAM support I got esp32ecp5 working https://github.com/emard/esp32ecp5/tree/master/circuitpython
    emard
    @emard
    Do you have some better experience with circuitpython with orangecrab?
    Lawrie Griffiths
    @lawrie
    I only checked that the disk drive appeared and I could connect to it with /dev/ttyACM0. I have not really used it.
    The designer of the Blackice boards, @folknology, is active again and is producing an entry-level board with an ESP32-S2 and a up5k. It will be interesting to see how well that works.
    emard
    @emard
    Yes this part is great, it also appears on S2. I asked them to make second usb-serial ttyACM1 - TX/RX it would great then FT231X would go to history, but they said endpoint shortage and posponed until dynamic desciptor support starts working
    circuipython has no user code support for interrupt and threads/concurrency so our uftpd, osd and ide spi emulation won't run in "background"
    Lawrie Griffiths
    @lawrie
    Yes, I saw your previous comment on that and showed it to @folknology.
    emard
    @emard
    Best upgrade what I currenty can do is modified PCB to accept either ESP32 WROOM or WROVER-E. I made it on kicad, just comparing both pinous to check didn't I connect something wrong
    emard
    @emard
    https://github.com/emard/ulx3s here is 3D model for new PCB with WROVER-E module. It can still accept WROOM modules. Constraints around ESP32 had changed. GPIO16,17 no longer available
    emard
    @emard
    Maybe it's slightly off-topic, but do we have some vivadoless blink for artix7 or quartusless blink for cyclone5?
    David Shah
    @daveshah1
    artix7: https://github.com/daveshah1/nextpnr-xilinx/ (still only proof-of-concept grade)
    cyclone5: synth_intel_alm in Yosys can do synthesis but you still need Quartus for PnR at the moment
    emard
    @emard
    Thnx!! Is there also some nightly/monthly build binary tools downloads :)? Actually I got esp32ecp5 to program artix7 so I wanted to freeware compile jtag-spi artix7 passthru from openFPGALoader if possible.
    https://github.com/trabucayre/openFPGALoader/blob/master/spiOverJtag/xilinx_spiOverJtag.vhd#L1 would this one work? I could manually convert from vhdl to verilog if needed
    David Shah
    @daveshah1
    No, binary tools are not built as it is not intended for end users yet
    Lawrie Griffiths
    @lawrie
    I have tidied up the QL code, removed the BRAM option that wasn't working and the non-standard I/O ports, and implemented something like the correct pitch for the audio, but not the other audio options yet.
    emard
    @emard
    @lawrie super! btw is there "elite" for QL? I see here some dome https://www.youtube.com/watch?v=eYoTSGvWf78
    Lawrie Griffiths
    @lawrie
    I haven't seen a version of it.
    Lawrie Griffiths
    @lawrie
    I've done a bit more of the QL sound, but I don't know if I have it correct as I can't get any QL emulators to produce sound. uqlx on Linux runs but produces no sound. qemulator on Windows doesn't start for me. They seem the best of the emulators. Older ones for Windows didn't run correctly.
    @Dolu1990 has the new SMP version of SaxonSoc Linux running now and I am trying to build it. Only one core fits on his 12F (when using the open source tools). With Diamond it uses a lot less LUTs.
    emard
    @emard
    For QL sound it should be good_enough, some BEEP from basic works, QL games are very few and sound is mostly annoyhing, nothing like c64 or amiga.
    Lawrie Griffiths
    @lawrie
    As @pnru_gitlab produced a description of how the sound worked by analysing the 8049 source code, I wanted to try to get it roughly right.
    emard
    @emard
    well when sound analysys is already done it's ok to try something, I thought you already applied it. I'd like to try new saxonsoc! For me it only matters that it boots. if we can dig out some simple K&R style C compiler and cross-comple it to work on saxonsoc and there compile hello world in few seconds, that's wow! no need for gcc/clang, they would compile hello.c for hours :). Super for it's multiplatform compatibility for both diamond and trellis can be tested. I often make code for trellis and diamond and in the process many errors appear. Before I did the same for xilinx and altera also, even more bugs revealed
    Dolu1990
    @Dolu1990
    Notes, i havn't updated the opensource toolchain since a while, i have to try it
    Lawrie Griffiths
    @lawrie
    @emard buildroot seemed to have made a decision not to support a native compiler, so gcc and clang are not available as packages.
    The problem with using an older Unix compiler is that it would need a risc-v backend.
    emard
    @emard
    @Dolu1990 here's nigthly build for all platforms :) https://github.com/open-tool-forge/fpga-toolchain/releases
    @lawrie I see! OK if something "light" with backend appears, let's watch and take it when available
    Dolu1990
    @Dolu1990
    Hooo i didn't know this exist
    thanks ^^
    emard
    @emard
    There's also fresh openFPGALoader that supports our board too
    Paul Ruiz
    @pnru_gitlab
    @lawrie don't feel obliged to do anything with sound, just because I analyzed the ROM. As said, the QL is a sentimental journey for me and the analysis was its own reward. I've always been intrigued with the English micro-computer scene of the early 80's and how interesting hardware was built from two bits of string and a roll of sticky tape.
    Paul Ruiz
    @pnru_gitlab
    I am also intrigued by ULA's (Uncommitted Logic Arrays) which were - in my view - the FPGA's of the early 1980's. Outside of Texas Instruments in the US and Ferranti in the UK I did not see this concept - not sure why it did not catch on more. For those who are unfamiliar with ULA's, they are essentially chips with a "sea" of NAND gates and no metal layer. The customer specified a custom metal layer to complete the base chip; this was economic for runs of a few thousand units I think.
    Paul Ruiz
    @pnru_gitlab
    @emard, @lawrie: for a RISC_V compiler you could try to cross-compile this one:
    https://github.com/michg/riscv32_lcc
    LCC is only some 20,000 lines of source code (about 3 times the size of the PDP-11 C compiler) and there is a book that explains every line of it.
    emard
    @emard
    Ohoo, yes lcc compiler looks great, allows reasonably modern coding style. We can compile simple hardware examples like i2c RTC clock or SPI LCD displays.
    Lawrie Griffiths
    @lawrie
    I see that one of its targets is @Dolu1990's Murax SoC (as well as picorv32).
    Lawrie Griffiths
    @lawrie
    The new SaxonSoc is now working on a 12F for me. Here are the instructions to build from source - https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.1/bsp/radiona/ulx3s/smp
    There is no sdcard image at the moment, but all the files are there for you to build your own.
    Lawrie Griffiths
    @lawrie
    @pnru_gitlab @Dolu1990 asked these questions about using the SDRAM, which I thought you might know something about from all your recent work on SDRAM drivers:
    I'm thinking about the SDRAM
    currently, the soc is at 50 mhz, and the sdram run at 100 Mhz using DDR io
    but maybe we should quad pump the SDRAM, and doing some bootloader calibration to ajust read delays
    i'm just currently not sure what is the critical path of the SDRAM chip themself
    in other words "why they are specified to X frequancy and not more"
    Dolu1990
    @Dolu1990
    Moaaaar powaaaaaaaa
    emard
    @emard
    oooh yeea :)) if you want to push SDRAM near the edge and give it some heat, on selected designs it can push 133MHz chips to 180-200 MHz, fmax depends on each board. 12F performs better than 85F. Here's memtest https://github.com/emard/ulx3s-misc/tree/master/examples/sdram/memtest_mister shows results on DVI monitor and with BTNs can adjust phase shift dynamically and watch for errors.
    Dolu1990
    @Dolu1990
    <3
    Nice thanks :)
    So this test controle the shift of the clock sent to the DRAM ?