@lawrie @Dolu1990 I am not sure I understand the SDRAM questions. In any case, my latest version is here: https://gitlab.com/pnru/cortex/-/blob/master/sdram.v
In particular note new lines 45-47 - I am not sure why, but this mod generally pushes Fmax up to about 200MHz (it depends a bit on the NextPNR seed).
I am not sure what you mean by "using DDR io" - does the SDRAM chip on the ULX3S support DDR? Maybe you mean by DDR that it runs at twice the speed of the CPU or that it uses burst size 2?
I don't know what the critical path in the SDRAM chip is, but I do have a hypothesis. When working with a CAS delay of 3 clocks, the data really arrives after 2 clocks plus 6-7ns (spending on the speed grade). If you clock a grade 6 chip (PC166) faster, a clock cycle will take less than 6ns and the data will only arrive after the third rising clock edge. My guess is that the 6-7ns is related to the speed of the sense amplifiers or something like that.
If you clock a grade 6 chip (PC166) faster, a clock cycle will take less than 6ns and the data will only arrive after the third rising clock edge.
Hooo i see
cc -v hello.cyou can see the individual steps. First it runs the pre-processor (turning .c into .i) and then the c0 pass. This pass essentially converts C source into parse trees. This is followed by the c1 pass, which uses a tile covering algorithm to convert the parse trees into assembler (i.e. generating a .s file). Optionally, there is a c2 pass which does peephole and a few other optimizations. Then it runs the assembler 'as' to generate a relocatable object file (an .o file). As a last step it invokes the linker ld to combine this object file with routines from the C library and generating a static binary (the a.out file).