root@buildroot:~# cat /proc/cpuinfo processor : 0 hart : 1 isa : rv32im mmu : sv32 processor : 1 hart : 0 isa : rv32im mmu : sv32
Info: Device utilisation: Info: TRELLIS_SLICE: 15356/41820 36% Info: TRELLIS_IO: 83/ 365 22% Info: DCCA: 3/ 56 5% Info: DP16KD: 48/ 208 23% Info: MULT18X18D: 8/ 156 5% Info: ALU54B: 0/ 78 0% Info: EHXPLLL: 1/ 4 25% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 39/ 224 17% Info: SIOLOGIC: 0/ 141 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 1/ 1 100% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 14 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0%
@pnru_gitlab @emard I finished the QL sound with an attempt at everything (increments, wrap, random, fuzz), but I don't know how close to the original it is.
@lawrie That is cool! I think @Speccery has a working QL, maybe he can tell if the sound is anything like that of the original hardware. If we add write capability to the microdrive emulation it will be the best QL implementation on FPGA that I know of. Later in October I will have time to help with that.
@pnru_gitlab @emard I have started looking at riscv_lcc. It is not straightforward to cross-compile. Some parts (such as lburg) seem to be ...
@lawrie Here, too, I hope to have time in October to help on getting a tool chain in place that works for Risc-V systems. I would find it cool to see an ancient Unix running on a Risc-V CPU/system.
I can see that you would first build a cross-compiler with gcc and then a native one using the cross-compiler. The native build requires a matching C library. This may require some hand work to get right. I would expect that this C library does not need to be very big. If you get stuck with this, let me know and I'll see if I can figure it out.
@lawrie Had a quick try with lcc-riscv. It compiled for me on OSX, almost out of the box. The source has its own implementation of 'memmove' and this is a macro on today's OSX. So I needed to undef the macro just before the redefinition. Then it builds the cross compiler & tools.
Using the cross compiler is another matter. The core compiler and the assembler seem fine, but the linker/loader is troublesome - I think it is a work in progress. There are source files for the C library, but these build as a set of smaller libraries ("stdio.lib", "stdlib.lib", etc.) and are not combined into one big "libc.lib").
From the test code it seems that the work routine is to custom link files into a bare binary image and to put this binary image into the memory of a small nano-riscv system (verilog included in the test cases).
Probably the quickest way to proceed is to reach out to the author of that Git repo and see if he is interested in getting this stuff to work on SaxonSoc. In the alternative, rounding out the linker/loader does seem a doable amount of work.
@emard 'small' is relative. The cross compiler has >0.5MB of executable; that includes 4 backends (spare, mips, x86 and riscv32) but it will be >0.3MB for sure. Runtime memory use may be double that.
@lawrie @emard I did look a bit more at the toolchain. Compiler, assembler, archiver all appear to work fine. The utils appear to have roots in the ECO32 project: https://github.com/hgeisse/eco32
The riscv32 linker/loader seems to be a custom job. I managed to build a full libc.lib and could link a "hello world" program to an a.out file. That file is ~30KB, as it drags in much of stdio and of the floating point library routines.
As there is no OS, the C library just has stubs for some of the sys calls (https://github.com/michg/riscv32_lcc/blob/master/lcc/bin/libs/stdlib/syscall.c), with I/O hardcoded to a UART.
All in all, the compiler seems fine, but getting it to run on SaxonSoc is not a slam dunk.